309e1d8193
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
150 lines
3.9 KiB
C++
150 lines
3.9 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_TIMING_HH__
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#define __CPU_SIMPLE_TIMING_HH__
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#include "cpu/simple/base.hh"
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class TimingSimpleCPU : public BaseSimpleCPU
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{
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public:
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struct Params : public BaseSimpleCPU::Params {
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};
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TimingSimpleCPU(Params *params);
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virtual ~TimingSimpleCPU();
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virtual void init();
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public:
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//
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enum Status {
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Idle,
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Running,
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IcacheRetry,
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IcacheWaitResponse,
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IcacheWaitSwitch,
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DcacheRetry,
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DcacheWaitResponse,
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DcacheWaitSwitch,
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SwitchedOut
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};
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protected:
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Status _status;
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Status status() const { return _status; }
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private:
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class CpuPort : public Port
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{
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protected:
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TimingSimpleCPU *cpu;
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public:
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CpuPort(TimingSimpleCPU *_cpu)
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: cpu(_cpu)
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{ }
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protected:
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virtual Tick recvAtomic(Packet &pkt);
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virtual void recvFunctional(Packet &pkt);
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virtual void recvStatusChange(Status status);
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{ resp.clear(); snoop.clear(); }
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};
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class IcachePort : public CpuPort
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{
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public:
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IcachePort(TimingSimpleCPU *_cpu)
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: CpuPort(_cpu)
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{ }
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protected:
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virtual bool recvTiming(Packet &pkt);
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virtual Packet *recvRetry();
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};
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class DcachePort : public CpuPort
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{
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public:
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DcachePort(TimingSimpleCPU *_cpu)
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: CpuPort(_cpu)
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{ }
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protected:
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virtual bool recvTiming(Packet &pkt);
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virtual Packet *recvRetry();
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};
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IcachePort icachePort;
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DcachePort dcachePort;
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Packet *ifetch_pkt;
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Packet *dcache_pkt;
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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void switchOut(Sampler *s);
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void takeOverFrom(BaseCPU *oldCPU);
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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void fetch();
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void completeInst(Fault fault);
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void completeIfetch();
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void completeDataAccess(Packet *);
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};
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#endif // __CPU_SIMPLE_TIMING_HH__
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