gem5/cpu/SConscript
Steve Reinhardt 309e1d8193 Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 17:36:50 -04:00

143 lines
4.9 KiB
Python

# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import os.path
# Import build environment variable from SConstruct.
Import('env')
#################################################################
#
# Generate StaticInst execute() method signatures.
#
# There must be one signature for each CPU model compiled in.
# Since the set of compiled-in models is flexible, we generate a
# header containing the appropriate set of signatures on the fly.
#
#################################################################
# CPU model-specific data is contained in cpu_models.py
# Convert to SCons File node to get path handling
models_db = File('cpu_models.py')
# slurp in contents of file
execfile(models_db.srcnode().abspath)
# Template for execute() signature.
exec_sig_template = '''
virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
{ panic("initiateAcc not defined!"); };
virtual Fault completeAcc(Packet *pkt, %s *xc,
Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); };
'''
# Generate header.
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
print >> f, '''
#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
#define __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
for cpu in env['CPU_MODELS']:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
print >> f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
# Generate string that gets printed when header is rebuilt
def gen_sigs_string(target, source, env):
return "Generating static_inst_exec_sigs.hh: " \
+ ', '.join(env['CPU_MODELS'])
# Add command to generate header to environment.
env.Command('static_inst_exec_sigs.hh', models_db,
Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = ['CPU_MODELS']))
#################################################################
#
# Include CPU-model-specific files based on set of models
# specified in CPU_MODELS build option.
#
#################################################################
sources = []
need_simple_base = False
if 'AtomicSimpleCPU' in env['CPU_MODELS']:
need_simple_base = True
sources += Split('simple/atomic.cc')
if 'TimingSimpleCPU' in env['CPU_MODELS']:
need_simple_base = True
sources += Split('simple/timing.cc')
if need_simple_base:
sources += Split('simple/base.cc')
if 'FastCPU' in env['CPU_MODELS']:
sources += Split('fast/cpu.cc')
if 'AlphaFullCPU' in env['CPU_MODELS']:
sources += Split('''
o3/2bit_local_pred.cc
o3/alpha_dyn_inst.cc
o3/alpha_cpu.cc
o3/alpha_cpu_builder.cc
o3/bpred_unit.cc
o3/btb.cc
o3/commit.cc
o3/decode.cc
o3/fetch.cc
o3/free_list.cc
o3/cpu.cc
o3/iew.cc
o3/inst_queue.cc
o3/ldstq.cc
o3/mem_dep_unit.cc
o3/ras.cc
o3/rename.cc
o3/rename_map.cc
o3/rob.cc
o3/sat_counter.cc
o3/store_set.cc
o3/tournament_pred.cc
''')
# FullCPU sources are included from m5/SConscript since they're not
# below this point in the file hierarchy.
# Convert file names to SCons File objects. This takes care of the
# path relative to the top of the directory tree.
sources = [File(s) for s in sources]
Return('sources')