arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
369 lines
11 KiB
C++
369 lines
11 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <iostream>
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#include <string>
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#include <sstream>
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "sim/param.hh"
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#include "sim/sim_events.hh"
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#include "base/trace.hh"
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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#if FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), clock(p->clock), checkInterrupts(true),
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params(p), number_of_threads(p->numberOfThreads), system(p->system)
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#else
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), clock(p->clock), params(p),
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number_of_threads(p->numberOfThreads)
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#endif
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{
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DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
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this);
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if (number_of_threads > maxThreadsPerCPU)
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maxThreadsPerCPU = number_of_threads;
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// allocate per-thread instruction-based event queues
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comInstEventQueue = new EventQueue *[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comInstEventQueue[i] = new EventQueue("instruction-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_insts_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread,
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"a thread reached the max instruction count");
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if (p->max_insts_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comInstEventQueue[i],
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"all threads reached the max instruction count",
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p->max_insts_all_threads, *counter);
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}
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// allocate per-thread load-based event queues
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comLoadEventQueue = new EventQueue *[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comLoadEventQueue[i] = new EventQueue("load-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_loads_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread,
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"a thread reached the max load count");
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if (p->max_loads_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comLoadEventQueue[i],
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"all threads reached the max load count",
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p->max_loads_all_threads, *counter);
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}
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#if FULL_SYSTEM
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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#endif
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functionTracingEnabled = false;
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if (p->functionTrace) {
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functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = p->functionTraceStart;
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if (p->functionTraceStart == 0) {
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functionTracingEnabled = true;
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} else {
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Event *e =
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new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
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true);
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e->schedule(p->functionTraceStart);
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}
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}
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#if FULL_SYSTEM
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profileEvent = NULL;
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if (params->profile)
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profileEvent = new ProfileEvent(this, params->profile);
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#endif
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}
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BaseCPU::Params::Params()
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{
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#if FULL_SYSTEM
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profile = false;
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#endif
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}
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void
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BaseCPU::enableFunctionTrace()
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{
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functionTracingEnabled = true;
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}
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BaseCPU::~BaseCPU()
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{
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}
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void
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BaseCPU::init()
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{
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if (!params->deferRegistration)
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registerExecContexts();
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}
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void
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BaseCPU::startup()
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{
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#if FULL_SYSTEM
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if (!params->deferRegistration && profileEvent)
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profileEvent->schedule(curTick);
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#endif
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}
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void
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BaseCPU::regStats()
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{
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using namespace Stats;
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numCycles
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.name(name() + ".numCycles")
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.desc("number of cpu cycles simulated")
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;
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int size = execContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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execContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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execContexts[0]->regStats(name());
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}
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void
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BaseCPU::registerExecContexts()
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{
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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#if FULL_SYSTEM
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int id = params->cpu_id;
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if (id != -1)
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id += i;
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xc->cpu_id = system->registerExecContext(xc, id);
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#else
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xc->cpu_id = xc->process->registerExecContext(xc);
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#endif
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}
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}
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void
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BaseCPU::switchOut(Sampler *sampler)
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{
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panic("This CPU doesn't support sampling!");
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}
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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assert(execContexts.size() == oldCPU->execContexts.size());
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *newXC = execContexts[i];
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ExecContext *oldXC = oldCPU->execContexts[i];
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newXC->takeOverFrom(oldXC);
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assert(newXC->cpu_id == oldXC->cpu_id);
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#if FULL_SYSTEM
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system->replaceExecContext(newXC, newXC->cpu_id);
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#else
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assert(newXC->process == oldXC->process);
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newXC->process->replaceExecContext(newXC, newXC->cpu_id);
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#endif
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}
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#if FULL_SYSTEM
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for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
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interrupts[i] = oldCPU->interrupts[i];
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intstatus = oldCPU->intstatus;
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for (int i = 0; i < execContexts.size(); ++i)
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if (execContexts[i]->profile)
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execContexts[i]->profile->clear();
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if (profileEvent)
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profileEvent->schedule(curTick);
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#endif
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}
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#if FULL_SYSTEM
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BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
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: Event(&mainEventQueue), cpu(_cpu), interval(_interval)
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{ }
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void
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BaseCPU::ProfileEvent::process()
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{
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for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) {
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ExecContext *xc = cpu->execContexts[i];
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xc->profile->sample(xc->profileNode, xc->profilePC);
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}
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schedule(curTick + interval);
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}
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void
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BaseCPU::post_interrupt(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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checkInterrupts = true;
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interrupts[int_num] |= 1 << index;
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intstatus |= (ULL(1) << int_num);
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}
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void
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BaseCPU::clear_interrupt(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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interrupts[int_num] &= ~(1 << index);
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if (interrupts[int_num] == 0)
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intstatus &= ~(ULL(1) << int_num);
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}
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void
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BaseCPU::clear_interrupts()
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{
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DPRINTF(Interrupt, "Interrupts all cleared\n");
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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}
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void
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BaseCPU::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
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SERIALIZE_SCALAR(intstatus);
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}
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void
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BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
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UNSERIALIZE_SCALAR(intstatus);
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}
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#endif // FULL_SYSTEM
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void
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BaseCPU::traceFunctionsInternal(Addr pc)
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{
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if (!debugSymbolTable)
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return;
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// if pc enters different function, print new function symbol and
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// update saved range. Otherwise do nothing.
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if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
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string sym_str;
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bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
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currentFunctionStart,
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currentFunctionEnd);
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if (!found) {
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// no symbol found: use addr as label
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sym_str = csprintf("0x%x", pc);
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currentFunctionStart = pc;
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currentFunctionEnd = pc + 1;
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}
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ccprintf(*functionTraceStream, " (%d)\n%d: %s",
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curTick - functionEntryTick, curTick, sym_str);
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functionEntryTick = curTick;
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}
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
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