368 lines
15 KiB
Python
368 lines
15 KiB
Python
# Copyright (c) 2010-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Brad Beckmann
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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import Ruby
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Simulation
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import CacheConfig
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import MemConfig
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from Caches import *
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import Options
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# Check if KVM support has been enabled, we might need to do VM
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# configuration if that's the case.
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have_kvm_support = 'BaseKvmCPU' in globals()
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def is_kvm_cpu(cpu_class):
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return have_kvm_support and cpu_class != None and \
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issubclass(cpu_class, BaseKvmCPU)
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def cmd_line_template():
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if options.command_line and options.command_line_file:
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print "Error: --command-line and --command-line-file are " \
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"mutually exclusive"
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sys.exit(1)
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if options.command_line:
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return options.command_line
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if options.command_line_file:
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return open(options.command_line_file).read().strip()
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return None
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def build_test_system(np):
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cmdline = cmd_line_template()
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
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cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
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options.ruby, cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode, options.machine_type,
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options.num_cpus, bm[0], options.dtb_filename,
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bare_metal=options.bare_metal,
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cmdline=cmdline,
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external_memory=options.external_memory_system)
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if options.enable_context_switch_stats_dump:
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test_sys.enable_context_switch_stats_dump = True
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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# Set the cache line size for the entire system
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test_sys.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain
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test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Create a source clock for the system and set the clock period
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test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = test_sys.voltage_domain)
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# Create a CPU voltage domain
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test_sys.cpu_voltage_domain = VoltageDomain()
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# Create a source clock for the CPUs and set the clock period
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test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain =
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test_sys.cpu_voltage_domain)
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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if options.script is not None:
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test_sys.readfile = options.script
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if options.lpae:
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test_sys.have_lpae = True
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if options.virtualisation:
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test_sys.have_virtualization = True
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test_sys.init_param = options.init_param
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# For now, assign all the CPUs to the same clock domain
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test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
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for i in xrange(np)]
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if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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if options.ruby:
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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Ruby.create_system(options, True, test_sys, test_sys.iobus,
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test_sys._dma_ports)
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# Create a seperate clock domain for Ruby
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test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = test_sys.voltage_domain)
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# Connect the ruby io port to the PIO bus,
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# assuming that there is just one such port.
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test_sys.iobus.master = test_sys.ruby._io_port.slave
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for (i, cpu) in enumerate(test_sys.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = test_sys.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
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cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
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cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
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cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
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else:
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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elif not options.external_memory_system:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem:
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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if options.simpoint_profile:
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if not options.fastmem:
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# Atomic CPU checked with fastmem option already
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fatal("SimPoint generation should be done with atomic cpu and fastmem")
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if np > 1:
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fatal("SimPoint generation not supported with more than one CPUs")
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.simpoint_profile:
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test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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# If elastic tracing is enabled when not restoring from checkpoint and
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# when not fast forwarding using the atomic cpu, then check that the
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# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
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# passes then attach the elastic trace probe.
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# If restoring from checkpoint or fast forwarding, the code that does this for
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# FutureCPUClass is in the Simulation module. If the check passes then the
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# elastic trace probe is attached to the switch CPUs.
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if options.elastic_trace_en and options.checkpoint_restore == None and \
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not options.fast_forward:
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CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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return test_sys
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def build_drive_system(np):
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# driver system CPU is always simple, so is the memory
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# Note this is an assignment of a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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DriveMemClass = SimpleMemory
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cmdline = cmd_line_template()
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if buildEnv['TARGET_ISA'] == 'alpha':
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == 'mips':
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drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == 'sparc':
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == 'x86':
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drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
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cmdline=cmdline)
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elif buildEnv['TARGET_ISA'] == 'arm':
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drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
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bm[1], options.dtb_filename, cmdline=cmdline)
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# Create a top-level voltage domain
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drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Create a source clock for the system and set the clock period
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drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = drive_sys.voltage_domain)
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# Create a CPU voltage domain
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drive_sys.cpu_voltage_domain = VoltageDomain()
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# Create a source clock for the CPUs and set the clock period
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drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain =
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drive_sys.cpu_voltage_domain)
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drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
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cpu_id=0)
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drive_sys.cpu.createThreads()
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drive_sys.cpu.createInterruptController()
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drive_sys.cpu.connectAllPorts(drive_sys.membus)
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if options.fastmem:
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drive_sys.cpu.fastmem = True
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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if is_kvm_cpu(DriveCPUClass):
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drive_sys.vm = KvmVM()
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drive_sys.iobridge = Bridge(delay='50ns',
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ranges = drive_sys.mem_ranges)
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drive_sys.iobridge.slave = drive_sys.iobus.master
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drive_sys.iobridge.master = drive_sys.membus.slave
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# Create the appropriate memory controllers and connect them to the
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# memory bus
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drive_sys.mem_ctrls = [DriveMemClass(range = r)
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for r in drive_sys.mem_ranges]
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for i in xrange(len(drive_sys.mem_ctrls)):
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drive_sys.mem_ctrls[i].port = drive_sys.membus.master
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drive_sys.init_param = options.init_param
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return drive_sys
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# Add options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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# Match the memories with the CPUs, based on the options for the test system
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TestMemClass = Simulation.setMemClass(options)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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if options.dual:
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bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
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mem=options.mem_size, os_type=options.os_type),
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SysConfig(disk=options.disk_image, rootdev=options.root_device,
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mem=options.mem_size, os_type=options.os_type)]
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else:
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bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
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mem=options.mem_size, os_type=options.os_type)]
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np = options.num_cpus
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test_sys = build_test_system(np)
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if len(bm) == 2:
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drive_sys = build_drive_system(np)
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root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1 and options.dist:
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# This system is part of a dist-gem5 simulation
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root = makeDistRoot(test_sys,
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options.dist_rank,
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options.dist_size,
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options.dist_server_name,
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options.dist_server_port,
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options.dist_sync_repeat,
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options.dist_sync_start,
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options.ethernet_linkspeed,
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options.ethernet_linkdelay,
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options.etherdump);
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elif len(bm) == 1:
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root = Root(full_system=True, system=test_sys)
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else:
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print "Error I don't know how to create more than 2 systems."
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sys.exit(1)
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if options.timesync:
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root.time_sync_enable = True
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if options.frame_capture:
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VncServer.frame_capture = True
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Simulation.setWorkCountOptions(test_sys, options)
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Simulation.run(options, root, test_sys, FutureClass)
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