92de70b69a
This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
330 lines
11 KiB
C++
330 lines
11 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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This file has been modified by Kevin Moore and Dan Nussbaum of the
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Scalable Systems Research Group at Sun Microsystems Laboratories
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(http://research.sun.com/scalable/) to support the Adaptive
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Transactional Memory Test Platform (ATMTP).
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Please send email to atmtp-interest@sun.com with feedback, questions, or
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to request future announcements about ATMTP.
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----------------------------------------------------------------------
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File modification date: 2008-02-23
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----------------------------------------------------------------------
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*/
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/*
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* Profiler.hh
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*
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* Description:
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*
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* $Id$
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*
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*/
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#ifndef PROFILER_H
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#define PROFILER_H
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#include "mem/ruby/libruby.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/protocol/GenericMachineType.hh"
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#include "mem/ruby/config/RubyConfig.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/AccessType.hh"
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#include "mem/ruby/system/NodeID.hh"
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/protocol/PrefetchBit.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Set.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/GenericRequestType.hh"
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#include "mem/ruby/system/MemoryControl.hh"
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class CacheMsg;
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class CacheProfiler;
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class AddressProfiler;
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template <class KEY_TYPE, class VALUE_TYPE> class Map;
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struct memory_control_profiler {
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long long int m_memReq;
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long long int m_memBankBusy;
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long long int m_memBusBusy;
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long long int m_memTfawBusy;
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long long int m_memReadWriteBusy;
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long long int m_memDataBusBusy;
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long long int m_memRefresh;
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long long int m_memRead;
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long long int m_memWrite;
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long long int m_memWaitCycles;
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long long int m_memInputQ;
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long long int m_memBankQ;
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long long int m_memArbWait;
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long long int m_memRandBusy;
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long long int m_memNotOld;
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Vector<long long int> m_memBankCount;
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int m_banks_per_rank;
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int m_ranks_per_dimm;
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int m_dimms_per_channel;
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};
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class Profiler : public Consumer {
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public:
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// Constructors
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Profiler(const string & name);
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void init(const vector<string> & argv, vector<string> memory_control_names);
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// Destructor
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~Profiler();
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// Public Methods
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void wakeup();
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void setPeriodicStatsFile(const string& filename);
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void setPeriodicStatsInterval(integer_t period);
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void printStats(ostream& out, bool short_stats=false);
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void printShortStats(ostream& out) { printStats(out, true); }
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void printTraceStats(ostream& out) const;
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void clearStats();
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void printConfig(ostream& out) const;
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void printResourceUsage(ostream& out) const;
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AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
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AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
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void addPrimaryStatSample(const CacheMsg& msg, NodeID id);
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void addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addAddressTraceSample(const CacheMsg& msg, NodeID id);
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void profileRequest(const string& requestStr);
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void profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner);
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void profileMulticastRetry(const Address& addr, int count);
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void profileFilterAction(int action);
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void profileConflictingRequests(const Address& addr);
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void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); }
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void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); }
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void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); }
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void countBAUnicast() { m_num_BA_unicasts++; }
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void countBABroadcast() { m_num_BA_broadcasts++; }
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void recordPrediction(bool wasGood, bool wasPredicted);
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void startTransaction(int cpu);
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void endTransaction(int cpu);
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void profilePFWait(Time waitTime);
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void controllerBusy(MachineID machID);
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void bankBusy();
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void missLatency(Time t, RubyRequestType type);
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void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach);
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void stopTableUsageSample(int num) { m_stopTableProfile.add(num); }
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void L1tbeUsageSample(int num) { m_L1tbeProfile.add(num); }
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void L2tbeUsageSample(int num) { m_L2tbeProfile.add(num); }
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void sequencerRequests(int num) { m_sequencer_requests.add(num); }
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void storeBuffer(int size, int blocks) { m_store_buffer_size.add(size); m_store_buffer_blocks.add(blocks);}
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void profileGetXMaskPrediction(const Set& pred_set);
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void profileGetSMaskPrediction(const Set& pred_set);
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void profileTrainingMask(const Set& pred_set);
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void profileTransition(const string& component, NodeID version, Address addr,
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const string& state, const string& event,
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const string& next_state, const string& note);
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void profileMsgDelay(int virtualNetwork, int delayCycles);
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void print(ostream& out) const;
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int64 getTotalInstructionsExecuted() const;
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int64 getTotalTransactionsExecuted() const;
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void rubyWatch(int proc);
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bool watchAddress(Address addr);
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// return Ruby's start time
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Time getRubyStartTime(){
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return m_ruby_start;
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}
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// added for MemoryControl:
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void profileMemReq(string name, int bank);
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void profileMemBankBusy(string name);
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void profileMemBusBusy(string name);
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void profileMemTfawBusy(string name);
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void profileMemReadWriteBusy(string name);
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void profileMemDataBusBusy(string name);
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void profileMemRefresh(string name);
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void profileMemRead(string name);
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void profileMemWrite(string name);
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void profileMemWaitCycles(string name, int cycles);
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void profileMemInputQ(string name, int cycles);
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void profileMemBankQ(string name, int cycles);
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void profileMemArbWait(string name, int cycles);
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void profileMemRandBusy(string name);
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void profileMemNotOld(string name);
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//added by SS
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bool getHotLines() { return m_hot_lines; }
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bool getAllInstructions() { return m_all_instructions; }
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private:
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//added by SS
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vector<string> m_memory_control_names;
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// Private Methods
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void addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addL1DStatSample(const CacheMsg& msg, NodeID id);
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void addL1IStatSample(const CacheMsg& msg, NodeID id);
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GenericRequestType CacheRequestType_to_GenericRequestType(const CacheRequestType& type);
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// Private copy constructor and assignment operator
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Profiler(const Profiler& obj);
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Profiler& operator=(const Profiler& obj);
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// Data Members (m_ prefix)
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CacheProfiler* m_L1D_cache_profiler_ptr;
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CacheProfiler* m_L1I_cache_profiler_ptr;
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CacheProfiler* m_L2_cache_profiler_ptr;
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AddressProfiler* m_address_profiler_ptr;
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AddressProfiler* m_inst_profiler_ptr;
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Vector<int64> m_instructions_executed_at_start;
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Vector<int64> m_cycles_executed_at_start;
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ostream* m_periodic_output_file_ptr;
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integer_t m_stats_period;
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Time m_ruby_start;
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time_t m_real_time_start_time;
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int m_num_BA_unicasts;
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int m_num_BA_broadcasts;
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Vector<integer_t> m_perProcTotalMisses;
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Vector<integer_t> m_perProcUserMisses;
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Vector<integer_t> m_perProcSupervisorMisses;
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Vector<integer_t> m_perProcStartTransaction;
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Vector<integer_t> m_perProcEndTransaction;
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Vector < Vector < integer_t > > m_busyControllerCount;
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integer_t m_busyBankCount;
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Histogram m_multicast_retry_histogram;
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Histogram m_L1tbeProfile;
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Histogram m_L2tbeProfile;
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Histogram m_stopTableProfile;
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Histogram m_filter_action_histogram;
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Histogram m_tbeProfile;
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Histogram m_sequencer_requests;
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Histogram m_store_buffer_size;
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Histogram m_store_buffer_blocks;
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Histogram m_read_sharing_histogram;
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Histogram m_write_sharing_histogram;
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Histogram m_all_sharing_histogram;
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int64 m_cache_to_cache;
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int64 m_memory_to_cache;
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Histogram m_prefetchWaitHistogram;
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Vector<Histogram> m_missLatencyHistograms;
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Vector<Histogram> m_machLatencyHistograms;
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Histogram m_L2MissLatencyHistogram;
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Histogram m_allMissLatencyHistogram;
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Histogram m_allSWPrefetchLatencyHistogram;
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Histogram m_SWPrefetchL2MissLatencyHistogram;
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Vector<Histogram> m_SWPrefetchLatencyHistograms;
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Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
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Histogram m_delayedCyclesHistogram;
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Histogram m_delayedCyclesNonPFHistogram;
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Vector<Histogram> m_delayedCyclesVCHistograms;
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int m_predictions;
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int m_predictionOpportunities;
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int m_goodPredictions;
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Histogram m_gets_mask_prediction;
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Histogram m_getx_mask_prediction;
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Histogram m_explicit_training_mask;
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// For profiling possibly conflicting requests
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Map<Address, Time>* m_conflicting_map_ptr;
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Histogram m_conflicting_histogram;
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Histogram m_outstanding_requests;
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Histogram m_outstanding_persistent_requests;
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Histogram m_average_latency_estimate;
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Map<Address, int>* m_watch_address_list_ptr;
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// counts all initiated cache request including PUTs
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int m_requests;
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Map <string, int>* m_requestProfileMap_ptr;
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// added for MemoryControl:
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//added by SS
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map< string, memory_control_profiler* > m_memory_control_profilers;
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//added by SS
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bool m_hot_lines;
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bool m_all_instructions;
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string m_name;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const Profiler& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const Profiler& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //PROFILER_H
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