a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
70 lines
3 KiB
C++
70 lines
3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/trace.hh"
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#include "cpu/o3/free_list.hh"
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SimpleFreeList::SimpleFreeList(unsigned activeThreads,
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unsigned _numLogicalIntRegs,
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unsigned _numPhysicalIntRegs,
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unsigned _numLogicalFloatRegs,
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unsigned _numPhysicalFloatRegs)
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: numLogicalIntRegs(_numLogicalIntRegs),
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numPhysicalIntRegs(_numPhysicalIntRegs),
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numLogicalFloatRegs(_numLogicalFloatRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs),
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numPhysicalRegs(numPhysicalIntRegs + numPhysicalFloatRegs)
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{
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DPRINTF(FreeList, "Creating new free list object.\n");
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// Put all of the extra physical registers onto the free list. This
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// means excluding all of the base logical registers.
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for (PhysRegIndex i = numLogicalIntRegs * activeThreads;
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i < numPhysicalIntRegs; ++i)
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{
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freeIntRegs.push(i);
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}
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// Put all of the extra physical registers onto the free list. This
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// means excluding all of the base logical registers. Because the
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// float registers' indices start where the physical registers end,
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// some math must be done to determine where the free registers start.
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PhysRegIndex i = numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
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for ( ; i < numPhysicalRegs; ++i)
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{
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freeFloatRegs.push(i);
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}
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}
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std::string
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SimpleFreeList::name() const
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{
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return "cpu.freelist";
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}
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