This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
392 lines
10 KiB
C++
392 lines
10 KiB
C++
/*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __CPU_SIMPLE_THREAD_HH__
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#define __CPU_SIMPLE_THREAD_HH__
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#include "arch/isa.hh"
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#include "arch/isa_traits.hh"
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#include "arch/registers.hh"
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#include "arch/tlb.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/eventq.hh"
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#include "sim/serialize.hh"
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class BaseCPU;
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#if FULL_SYSTEM
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#include "sim/system.hh"
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class FunctionProfile;
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class ProfileNode;
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class FunctionalPort;
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class PhysicalPort;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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};
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};
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#else // !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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class TranslatingPort;
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#endif // FULL_SYSTEM
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/**
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* The SimpleThread object provides a combination of the ThreadState
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* object and the ThreadContext interface. It implements the
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* ThreadContext interface so that a ProxyThreadContext class can be
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* made using SimpleThread as the template parameter (see
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* thread_context.hh). It adds to the ThreadState object by adding all
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* the objects needed for simple functional execution, including a
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* simple architectural register file, and pointers to the ITB and DTB
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* in full system mode. For CPU models that do not need more advanced
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* ways to hold state (i.e. a separate physical register file, or
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* separate fetch and commit PC's), this SimpleThread class provides
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* all the necessary state for full architecture-level functional
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* simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
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* examples.
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*/
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class SimpleThread : public ThreadState
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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public:
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typedef ThreadContext::Status Status;
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protected:
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union {
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FloatReg f[TheISA::NumFloatRegs];
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FloatRegBits i[TheISA::NumFloatRegs];
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} floatRegs;
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TheISA::IntReg intRegs[TheISA::NumIntRegs];
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TheISA::ISA isa; // one "instance" of the current ISA.
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TheISA::PCState _pcState;
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/** Did this instruction execute or is it predicated false */
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bool predicate;
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public:
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// pointer to CPU associated with this SimpleThread
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BaseCPU *cpu;
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ProxyThreadContext<SimpleThread> *tc;
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System *system;
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TheISA::TLB *itb;
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TheISA::TLB *dtb;
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// constructor: initialize SimpleThread from given process structure
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#if FULL_SYSTEM
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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TheISA::TLB *_itb, TheISA::TLB *_dtb,
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bool use_kernel_stats = true);
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#else
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SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
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TheISA::TLB *_itb, TheISA::TLB *_dtb);
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#endif
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SimpleThread();
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virtual ~SimpleThread();
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virtual void takeOverFrom(ThreadContext *oldContext);
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void regStats(const std::string &name);
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void copyTC(ThreadContext *context);
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void copyState(ThreadContext *oldContext);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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/***************************************************************
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* SimpleThread functions to provide CPU with access to various
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* state.
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**************************************************************/
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/** Returns the pointer to this SimpleThread's ThreadContext. Used
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* when a ThreadContext must be passed to objects outside of the
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* CPU.
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*/
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ThreadContext *getTC() { return tc; }
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void demapPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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dtb->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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dtb->demapPage(vaddr, asn);
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}
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#if FULL_SYSTEM
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void dumpFuncProfile();
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Fault hwrei();
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bool simPalCheck(int palFunc);
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#endif
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/*******************************************
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* ThreadContext interface functions.
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******************************************/
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BaseCPU *getCpuPtr() { return cpu; }
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TheISA::TLB *getITBPtr() { return itb; }
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TheISA::TLB *getDTBPtr() { return dtb; }
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System *getSystemPtr() { return system; }
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#if FULL_SYSTEM
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FunctionalPort *getPhysPort() { return physPort; }
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/** Return a virtual port. This port cannot be cached locally in an object.
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* After a CPU switch it may point to the wrong memory object which could
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* mean stale data.
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*/
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VirtualPort *getVirtPort() { return virtPort; }
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#endif
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Status status() const { return _status; }
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void setStatus(Status newStatus) { _status = newStatus; }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Halted.
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void halt();
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virtual bool misspeculating();
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void copyArchRegs(ThreadContext *tc);
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void clearArchRegs()
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{
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_pcState = 0;
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memset(intRegs, 0, sizeof(intRegs));
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memset(floatRegs.i, 0, sizeof(floatRegs.i));
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isa.clear();
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}
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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uint64_t regVal = intRegs[flatIndex];
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DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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FloatReg readFloatReg(int reg_idx)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatReg regVal = floatRegs.f[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
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reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
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return regVal;
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}
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FloatRegBits readFloatRegBits(int reg_idx)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatRegBits regVal = floatRegs.i[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
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reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
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return regVal;
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}
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void setIntReg(int reg_idx, uint64_t val)
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{
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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intRegs[flatIndex] = val;
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}
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void setFloatReg(int reg_idx, FloatReg val)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.f[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
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reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
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}
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.i[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
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reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
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}
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TheISA::PCState
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pcState()
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{
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return _pcState;
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}
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void
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pcState(const TheISA::PCState &val)
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{
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_pcState = val;
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}
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Addr
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instAddr()
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{
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return _pcState.instAddr();
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}
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Addr
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nextInstAddr()
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{
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return _pcState.nextInstAddr();
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}
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MicroPC
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microPC()
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{
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return _pcState.microPC();
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}
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bool readPredicate()
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{
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return predicate;
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}
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void setPredicate(bool val)
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{
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predicate = val;
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
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{
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return isa.readMiscRegNoEffect(misc_reg);
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}
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MiscReg
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readMiscReg(int misc_reg, ThreadID tid = 0)
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{
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return isa.readMiscReg(misc_reg, tc);
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}
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa.setMiscRegNoEffect(misc_reg, val);
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}
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa.setMiscReg(misc_reg, val, tc);
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}
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int
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flattenIntIndex(int reg)
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{
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return isa.flattenIntIndex(reg);
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}
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int
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flattenFloatIndex(int reg)
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{
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return isa.flattenFloatIndex(reg);
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}
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unsigned readStCondFailures() { return storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ storeCondFailures = sc_failures; }
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#if !FULL_SYSTEM
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void syscall(int64_t callnum)
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{
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process->syscall(callnum, tc);
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}
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#endif
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};
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// for non-speculative execution context, spec_mode is always false
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inline bool
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SimpleThread::misspeculating()
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{
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return false;
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}
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#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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