2fb632dbda
branch prediction, and makes memory dependence work properly. SConscript: Added return address stack, tournament predictor. cpu/base_cpu.cc: Added debug break and print statements. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Comment out possibly unneeded variables. cpu/beta_cpu/2bit_local_pred.cc: 2bit predictor no longer speculatively updates itself. cpu/beta_cpu/alpha_dyn_inst.hh: Comment formatting. cpu/beta_cpu/alpha_full_cpu.hh: Formatting cpu/beta_cpu/alpha_full_cpu_builder.cc: Added new parameters for branch predictors, and IQ parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Register stats. cpu/beta_cpu/alpha_params.hh: Added parameters for IQ, branch predictors, and store sets. cpu/beta_cpu/bpred_unit.cc: Removed one class. cpu/beta_cpu/bpred_unit.hh: Add in RAS, stats. Changed branch predictor unit functionality so that it holds a history of past branches so it can update, and also hold a proper history of the RAS so it can be restored on branch mispredicts. cpu/beta_cpu/bpred_unit_impl.hh: Added in stats, history of branches, RAS. Now bpred unit actually modifies the instruction's predicted next PC. cpu/beta_cpu/btb.cc: Add in sanity checks. cpu/beta_cpu/comm.hh: Add in communication where needed, remove it where it's not. cpu/beta_cpu/commit.hh: cpu/beta_cpu/rename.hh: cpu/beta_cpu/rename_impl.hh: Add in stats. cpu/beta_cpu/commit_impl.hh: Stats, update what is sent back on branch mispredict. cpu/beta_cpu/cpu_policy.hh: Change the bpred unit being used. cpu/beta_cpu/decode.hh: cpu/beta_cpu/decode_impl.hh: Stats. cpu/beta_cpu/fetch.hh: Stats, change squash so it can handle squashes from decode differently than squashes from commit. cpu/beta_cpu/fetch_impl.hh: Add in stats. Change how a cache line is fetched. Update to work with caches. Also have separate functions for different behavior if squash is coming from decode vs commit. cpu/beta_cpu/free_list.hh: Remove some old comments. cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/full_cpu.hh: Added function to remove instructions from back of instruction list until a certain sequence number. cpu/beta_cpu/iew.hh: Stats, separate squashing behavior due to branches vs memory. cpu/beta_cpu/iew_impl.hh: Stats, separate squashing behavior for branches vs memory. cpu/beta_cpu/inst_queue.cc: Debug stuff cpu/beta_cpu/inst_queue.hh: Stats, change how mem dep unit works, debug stuff cpu/beta_cpu/inst_queue_impl.hh: Stats, change how mem dep unit works, debug stuff. Also add in parameters that used to be hardcoded. cpu/beta_cpu/mem_dep_unit.hh: cpu/beta_cpu/mem_dep_unit_impl.hh: Add in stats, change how memory dependence unit works. It now holds the memory instructions that are waiting for their memory dependences to resolve. It provides which instructions are ready directly to the IQ. cpu/beta_cpu/regfile.hh: Fix up sanity checks. cpu/beta_cpu/rename_map.cc: Fix loop variable type. cpu/beta_cpu/rob_impl.hh: Remove intermediate DynInstPtr cpu/beta_cpu/store_set.cc: Add in debugging statements. cpu/beta_cpu/store_set.hh: Reorder function arguments to match the rest of the calls. --HG-- extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
253 lines
6.9 KiB
C++
253 lines
6.9 KiB
C++
// Todo: Find all the stuff in ExecContext and ev5 that needs to be
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// specifically designed for this CPU.
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// Read and write are horribly hacked up between not being sure where to
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// copy their code from, and Ron's memory changes.
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#ifndef __ALPHA_FULL_CPU_HH__
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#define __ALPHA_FULL_CPU_HH__
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// To include: comm, full cpu, ITB/DTB if full sys,
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//#include "cpu/beta_cpu/comm.hh"
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//#include "cpu/beta_cpu/alpha_impl.hh"
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#include "cpu/beta_cpu/full_cpu.hh"
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using namespace std;
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template <class Impl>
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class AlphaFullCPU : public FullBetaCPU<Impl>
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{
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public:
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typedef typename Impl::ISA AlphaISA;
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typedef typename Impl::Params Params;
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public:
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AlphaFullCPU(Params ¶ms);
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#ifdef FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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#endif
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public:
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void regStats();
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#ifdef FULL_SYSTEM
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bool inPalMode();
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//Note that the interrupt stuff from the base CPU might be somewhat
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//ISA specific (ie NumInterruptLevels). These functions might not
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//be needed in FullCPU though.
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// void post_interrupt(int int_num, int index);
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// void clear_interrupt(int int_num, int index);
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// void clear_interrupts();
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Fault translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return No_Fault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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// Later on may want to remove this misc stuff from the regfile and
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// have it handled at this level. Might prove to be an issue when
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// trying to rename source/destination registers...
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uint64_t readUniq()
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{
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return regFile.readUniq();
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}
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void setUniq(uint64_t val)
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{
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regFile.setUniq(val);
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}
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uint64_t readFpcr()
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{
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return regFile.readFpcr();
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}
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void setFpcr(uint64_t val)
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{
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regFile.setFpcr(val);
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}
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#ifdef FULL_SYSTEM
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uint64_t *getIPR();
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uint64_t readIpr(int idx, Fault &fault);
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Fault setIpr(int idx, uint64_t val);
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int readIntrFlag();
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void setIntrFlag(int val);
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Fault hwrei();
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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void processInterrupts();
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#endif
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#ifndef FULL_SYSTEM
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// Need to change these into regfile calls that directly set a certain
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// register. Actually, these functions should handle most of this
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// functionality by themselves; should look up the rename and then
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// set the register.
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IntReg getSyscallArg(int i)
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{
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return xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
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}
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// used to shift args for indirect syscall
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void setSyscallArg(int i, IntReg val)
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{
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xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
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}
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void setSyscallReturn(int64_t return_value)
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{
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// check for error condition. Alpha syscall convention is to
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// indicate success/failure in reg a3 (r19) and put the
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// return value itself in the standard return value reg (v0).
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const int RegA3 = 19; // only place this is used
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if (return_value >= 0) {
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// no error
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xc->regs.intRegFile[RegA3] = 0;
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xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
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} else {
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// got an error, return details
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xc->regs.intRegFile[RegA3] = (IntReg) -1;
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xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
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}
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}
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void syscall();
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void squashStages();
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#endif
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void copyToXC();
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void copyFromXC();
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public:
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#ifdef FULL_SYSTEM
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bool palShadowEnabled;
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// Not sure this is used anywhere.
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void intr_post(RegFile *regs, Fault fault, Addr pc);
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// Actually used within exec files. Implement properly.
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void swap_palshadow(RegFile *regs, bool use_shadow);
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// Called by CPU constructor. Can implement as I please.
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void initCPU(RegFile *regs);
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// Called by initCPU. Implement as I please.
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void initIPRs(RegFile *regs);
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#endif
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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if (req->flags & LOCKED) {
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MiscRegFile *cregs = &req->xc->regs.miscRegs;
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cregs->lock_addr = req->paddr;
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cregs->lock_flag = true;
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}
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#endif
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Fault error;
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error = mem->read(req, data);
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data = htoa(data);
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return error;
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}
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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MiscRegFile *cregs;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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cregs = &xc->regs.miscRegs;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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req->xc->storeCondFailures = 0;//Needed? [RGD]
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} else {
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req->result = cregs->lock_flag;
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if (!cregs->lock_flag ||
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((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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cregs->lock_flag = false;
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if (((++req->xc->storeCondFailures) % 100000) == 0) {
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std::cerr << "Warning: "
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<< req->xc->storeCondFailures
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<< " consecutive store conditional failures "
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<< "on cpu " << cpu_id
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<< std::endl;
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}
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return No_Fault;
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}
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else req->xc->storeCondFailures = 0;
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < system->execContexts.size(); i++){
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cregs = &system->execContexts[i]->regs.miscRegs;
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if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
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cregs->lock_flag = false;
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}
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}
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#endif
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return mem->write(req, (T)htoa(data));
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}
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};
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#endif // __ALPHA_FULL_CPU_HH__
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