177 lines
7.7 KiB
Python
177 lines
7.7 KiB
Python
# Copyright (c) 2012-2013, 2015 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Lisa Hsu
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# Configure the M5 cache hierarchy config in one place
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#
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import m5
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from m5.objects import *
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from Caches import *
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def config_cache(options, system):
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if options.external_memory_system and (options.caches or options.l2cache):
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print "External caches and internal caches are exclusive options.\n"
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sys.exit(1)
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if options.external_memory_system:
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ExternalCache = ExternalCacheFactory(options.external_memory_system)
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if options.cpu_type == "arm_detailed":
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try:
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from O3_ARM_v7a import *
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except:
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print "arm_detailed is unavailable. Did you compile the O3 model?"
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sys.exit(1)
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dcache_class, icache_class, l2_cache_class = \
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O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
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else:
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dcache_class, icache_class, l2_cache_class = \
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L1_DCache, L1_ICache, L2Cache
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# Set the cache line size of the system
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system.cache_line_size = options.cacheline_size
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# If elastic trace generation is enabled, make sure the memory system is
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# minimal so that compute delays do not include memory access latencies.
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# Configure the compulsory L1 caches for the O3CPU, do not configure
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# any more caches.
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if options.l2cache and options.elastic_trace_en:
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fatal("When elastic trace is enabled, do not configure L2 caches.")
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if options.l2cache:
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# Provide a clock for the L2 and the L1-to-L2 bus here as they
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# are not connected using addTwoLevelCacheHierarchy. Use the
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# same clock as the CPUs.
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system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
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size=options.l2_size,
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assoc=options.l2_assoc)
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system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
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system.l2.cpu_side = system.tol2bus.master
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system.l2.mem_side = system.membus.slave
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if options.memchecker:
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system.memchecker = MemChecker()
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for i in xrange(options.num_cpus):
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if options.caches:
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icache = icache_class(size=options.l1i_size,
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assoc=options.l1i_assoc)
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dcache = dcache_class(size=options.l1d_size,
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assoc=options.l1d_assoc)
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if options.memchecker:
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dcache_mon = MemCheckerMonitor(warn_only=True)
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dcache_real = dcache
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# Do not pass the memchecker into the constructor of
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# MemCheckerMonitor, as it would create a copy; we require
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# exactly one MemChecker instance.
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dcache_mon.memchecker = system.memchecker
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# Connect monitor
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dcache_mon.mem_side = dcache.cpu_side
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# Let CPU connect to monitors
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dcache = dcache_mon
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# When connecting the caches, the clock is also inherited
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# from the CPU in question
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if buildEnv['TARGET_ISA'] == 'x86':
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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PageTableWalkerCache(),
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PageTableWalkerCache())
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else:
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
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if options.memchecker:
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# The mem_side ports of the caches haven't been connected yet.
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# Make sure connectAllPorts connects the right objects.
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system.cpu[i].dcache = dcache_real
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system.cpu[i].dcache_mon = dcache_mon
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elif options.external_memory_system:
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# These port names are presented to whatever 'external' system
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# gem5 is connecting to. Its configuration will likely depend
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# on these names. For simplicity, we would advise configuring
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# it to use this naming scheme; if this isn't possible, change
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# the names below.
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i),
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ExternalCache("cpu%d.itb_walker_cache" % i),
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ExternalCache("cpu%d.dtb_walker_cache" % i))
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else:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i))
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system.cpu[i].createInterruptController()
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if options.l2cache:
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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elif options.external_memory_system:
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system.cpu[i].connectUncachedPorts(system.membus)
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else:
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system.cpu[i].connectAllPorts(system.membus)
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return system
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# ExternalSlave provides a "port", but when that port connects to a cache,
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# the connecting CPU SimObject wants to refer to its "cpu_side".
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# The 'ExternalCache' class provides this adaptation by rewriting the name,
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# eliminating distracting changes elsewhere in the config code.
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class ExternalCache(ExternalSlave):
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def __getattr__(cls, attr):
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if (attr == "cpu_side"):
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attr = "port"
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return super(ExternalSlave, cls).__getattr__(attr)
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def __setattr__(cls, attr, value):
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if (attr == "cpu_side"):
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attr = "port"
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return super(ExternalSlave, cls).__setattr__(attr, value)
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def ExternalCacheFactory(port_type):
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def make(name):
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return ExternalCache(port_data=name, port_type=port_type,
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addr_ranges=[AllMemory])
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return make
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