10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
427 lines
48 KiB
Text
427 lines
48 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.793670 # Number of seconds simulated
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sim_ticks 793670137000 # Number of ticks simulated
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final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 897110 # Simulator instruction rate (inst/s)
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host_op_rate 947381 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1252348386 # Simulator tick rate (ticks/s)
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host_mem_usage 231392 # Number of bytes of host memory used
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host_seconds 633.75 # Real time elapsed on the host
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sim_insts 568539335 # Number of instructions simulated
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sim_ops 600398272 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory
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system.physmem.bytes_written::total 159552 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 1587340274 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 568539335 # Number of instructions committed
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system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 1995305 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls
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system.cpu.num_int_insts 533522631 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read
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system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 219173606 # number of memory refs
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system.cpu.num_load_insts 148952593 # Number of load instructions
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system.cpu.num_store_insts 70221013 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1587340274 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 12 # number of replacements
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system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use
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system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits
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system.cpu.icache.overall_hits::total 570073883 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
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system.cpu.icache.overall_misses::total 643 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 433468 # number of replacements
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system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
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system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
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system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
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system.cpu.dcache.overall_misses::total 437564 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 418626 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2512 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.640218 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.016455 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.015470 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.672143 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 40 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 185478 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 185518 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 418626 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 418626 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 225913 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 225913 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 40 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 411391 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 411431 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 411431 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26776 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 2493 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|