646994e599
Not sure what went wrong in the pushing of the Ruby patches, but somehow these regressions are not updated.
756 lines
84 KiB
Text
756 lines
84 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000096 # Number of seconds simulated
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sim_ticks 95773 # Number of ticks simulated
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final_tick 95773 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 67382 # Simulator instruction rate (inst/s)
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host_op_rate 67372 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1009646 # Simulator tick rate (ticks/s)
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host_mem_usage 452992 # Number of bytes of host memory used
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host_seconds 0.09 # Real time elapsed on the host
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sim_insts 6390 # Number of instructions simulated
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sim_ops 6390 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1 # Clock period in ticks
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system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74176 # Number of bytes read from this memory
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system.mem_ctrls.bytes_read::total 74176 # Number of bytes read from this memory
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system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
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system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory
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system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # Number of read requests responded to by this memory
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system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory
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system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
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system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
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system.mem_ctrls.bw_read::ruby.dir_cntrl0 774498032 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_read::total 774498032 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::ruby.dir_cntrl0 147014294 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::total 147014294 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_total::ruby.dir_cntrl0 921512326 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.bw_total::total 921512326 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.readReqs 1159 # Number of read requests accepted
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system.mem_ctrls.writeReqs 220 # Number of write requests accepted
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system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue
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system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
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system.mem_ctrls.bytesReadDRAM 63936 # Total number of bytes read from DRAM
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system.mem_ctrls.bytesReadWrQ 10240 # Total number of bytes read from write queue
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system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
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system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side
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system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
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system.mem_ctrls.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
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system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one
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system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::4 98 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::10 54 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::5 5 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
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system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
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system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
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system.mem_ctrls.totGap 95693 # Total gap between requests
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system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::6 1159 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
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system.mem_ctrls.rdQLenPdf::0 999 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.mem_ctrls.bytesPerActivate::samples 190 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::mean 358.736842 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::gmean 222.774947 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::stdev 335.486260 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::0-127 51 26.84% 26.84% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::128-255 50 26.32% 53.16% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::256-383 20 10.53% 63.68% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::384-511 14 7.37% 71.05% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::512-639 13 6.84% 77.89% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::640-767 7 3.68% 81.58% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 85.79% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::896-1023 4 2.11% 87.89% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::1024-1151 23 12.11% 100.00% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::total 190 # Bytes accessed per row activation
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system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::mean 140.600000 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::gmean 106.599883 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::stdev 79.767161 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
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system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
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system.mem_ctrls.totQLat 6604 # Total ticks spent queuing
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system.mem_ctrls.totMemAccLat 25585 # Total ticks spent from burst creation until serviced by the DRAM
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system.mem_ctrls.totBusLat 4995 # Total ticks spent in databus transfers
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system.mem_ctrls.avgQLat 6.61 # Average queueing delay per DRAM burst
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system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
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system.mem_ctrls.avgMemAccLat 25.61 # Average memory access latency per DRAM burst
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system.mem_ctrls.avgRdBW 667.58 # Average DRAM read bandwidth in MiByte/s
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system.mem_ctrls.avgWrBW 57.47 # Average achieved write bandwidth in MiByte/s
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system.mem_ctrls.avgRdBWSys 774.50 # Average system read bandwidth in MiByte/s
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system.mem_ctrls.avgWrBWSys 147.01 # Average system write bandwidth in MiByte/s
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system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.mem_ctrls.busUtil 5.66 # Data bus utilization in percentage
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system.mem_ctrls.busUtilRead 5.22 # Data bus utilization in percentage for reads
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system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes
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system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.mem_ctrls.avgWrQLen 21.87 # Average write queue length when enqueuing
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system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
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system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes
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system.mem_ctrls.readRowHitRate 80.78 # Row buffer hit rate for reads
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system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes
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system.mem_ctrls.avgGap 69.39 # Average gap between requests
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system.mem_ctrls.pageHitRate 79.73 # Row buffer hit rate, read and write combined
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system.mem_ctrls_0.actEnergy 483840 # Energy for activate commands per rank (pJ)
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system.mem_ctrls_0.preEnergy 268800 # Energy for precharge commands per rank (pJ)
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system.mem_ctrls_0.readEnergy 5129280 # Energy for read commands per rank (pJ)
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system.mem_ctrls_0.writeEnergy 290304 # Energy for write commands per rank (pJ)
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system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
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system.mem_ctrls_0.actBackEnergy 54966924 # Energy for active background per rank (pJ)
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system.mem_ctrls_0.preBackEnergy 7998600 # Energy for precharge background per rank (pJ)
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system.mem_ctrls_0.totalEnergy 75240468 # Total energy per rank (pJ)
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system.mem_ctrls_0.averagePower 803.061820 # Core power per rank (mW)
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system.mem_ctrls_0.memoryStateTime::IDLE 13501 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::ACT 77563 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ)
|
|
system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ)
|
|
system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ)
|
|
system.mem_ctrls_1.writeEnergy 601344 # Energy for write commands per rank (pJ)
|
|
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
|
system.mem_ctrls_1.actBackEnergy 61807608 # Energy for active background per rank (pJ)
|
|
system.mem_ctrls_1.preBackEnergy 1998600 # Energy for precharge background per rank (pJ)
|
|
system.mem_ctrls_1.totalEnergy 79043952 # Total energy per rank (pJ)
|
|
system.mem_ctrls_1.averagePower 843.648426 # Core power per rank (mW)
|
|
system.mem_ctrls_1.memoryStateTime::IDLE 2911 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::ACT 87676 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 1183 # DTB read hits
|
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 1190 # DTB read accesses
|
|
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
system.cpu.dtb.data_hits 2048 # DTB hits
|
|
system.cpu.dtb.data_misses 10 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 2058 # DTB accesses
|
|
system.cpu.itb.fetch_hits 6401 # ITB hits
|
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 6418 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.numCycles 95773 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 6390 # Number of instructions committed
|
|
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 6317 # number of integer instructions
|
|
system.cpu.num_fp_insts 10 # number of float instructions
|
|
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 2058 # number of memory refs
|
|
system.cpu.num_load_insts 1190 # Number of load instructions
|
|
system.cpu.num_store_insts 868 # Number of store instructions
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 95773 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu.Branches 1050 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 6400 # Class of executed instruction
|
|
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
system.ruby.outstanding_req_hist::bucket_size 1
|
|
system.ruby.outstanding_req_hist::max_bucket 9
|
|
system.ruby.outstanding_req_hist::samples 8449
|
|
system.ruby.outstanding_req_hist::mean 1
|
|
system.ruby.outstanding_req_hist::gmean 1
|
|
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.outstanding_req_hist::total 8449
|
|
system.ruby.latency_hist::bucket_size 64
|
|
system.ruby.latency_hist::max_bucket 639
|
|
system.ruby.latency_hist::samples 8448
|
|
system.ruby.latency_hist::mean 10.336766
|
|
system.ruby.latency_hist::gmean 3.311568
|
|
system.ruby.latency_hist::stdev 22.755667
|
|
system.ruby.latency_hist | 8211 97.19% 97.19% | 225 2.66% 99.86% | 1 0.01% 99.87% | 0 0.00% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.latency_hist::total 8448
|
|
system.ruby.hit_latency_hist::bucket_size 2
|
|
system.ruby.hit_latency_hist::max_bucket 19
|
|
system.ruby.hit_latency_hist::samples 7289
|
|
system.ruby.hit_latency_hist::mean 2.278502
|
|
system.ruby.hit_latency_hist::gmean 2.102334
|
|
system.ruby.hit_latency_hist::stdev 1.645548
|
|
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.hit_latency_hist::total 7289
|
|
system.ruby.miss_latency_hist::bucket_size 64
|
|
system.ruby.miss_latency_hist::max_bucket 639
|
|
system.ruby.miss_latency_hist::samples 1159
|
|
system.ruby.miss_latency_hist::mean 61.015531
|
|
system.ruby.miss_latency_hist::gmean 57.685008
|
|
system.ruby.miss_latency_hist::stdev 27.944488
|
|
system.ruby.miss_latency_hist | 922 79.55% 79.55% | 225 19.41% 98.96% | 1 0.09% 99.05% | 0 0.00% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.miss_latency_hist::total 1159
|
|
system.ruby.Directory.incomplete_times 1158
|
|
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
|
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
|
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
|
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits
|
|
system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses
|
|
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
|
|
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
|
|
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
|
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
|
|
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
|
|
system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
|
|
system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
|
|
system.ruby.l1_cntrl0.fully_busy_cycles 34 # cycles for which number of transistions == max transitions
|
|
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
system.ruby.network.routers0.percent_links_utilized 4.682426
|
|
system.ruby.network.routers0.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers0.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers0.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers0.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers0.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers0.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers0.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers0.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.network.routers1.percent_links_utilized 4.682426
|
|
system.ruby.network.routers1.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers1.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers1.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers1.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers1.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers1.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers1.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers1.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.network.routers2.percent_links_utilized 4.682426
|
|
system.ruby.network.routers2.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers2.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers2.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers2.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers2.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers2.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers2.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers2.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.network.msg_count.Request_Control 3477
|
|
system.ruby.network.msg_count.Response_Data 3477
|
|
system.ruby.network.msg_count.Writeback_Data 660
|
|
system.ruby.network.msg_count.Writeback_Control 9627
|
|
system.ruby.network.msg_count.Unblock_Control 3477
|
|
system.ruby.network.msg_byte.Request_Control 27816
|
|
system.ruby.network.msg_byte.Response_Data 250344
|
|
system.ruby.network.msg_byte.Writeback_Data 47520
|
|
system.ruby.network.msg_byte.Writeback_Control 77016
|
|
system.ruby.network.msg_byte.Unblock_Control 27816
|
|
system.ruby.network.routers0.throttle0.link_utilization 6.042413
|
|
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers0.throttle1.link_utilization 3.322440
|
|
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.network.routers1.throttle0.link_utilization 3.322440
|
|
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.network.routers1.throttle1.link_utilization 6.042413
|
|
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers2.throttle0.link_utilization 6.042413
|
|
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159
|
|
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144
|
|
system.ruby.network.routers2.throttle1.link_utilization 3.322440
|
|
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159
|
|
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
|
|
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143
|
|
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 923
|
|
system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1159
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9272
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272
|
|
system.ruby.LD.latency_hist::bucket_size 64
|
|
system.ruby.LD.latency_hist::max_bucket 639
|
|
system.ruby.LD.latency_hist::samples 1183
|
|
system.ruby.LD.latency_hist::mean 22.748943
|
|
system.ruby.LD.latency_hist::gmean 7.555083
|
|
system.ruby.LD.latency_hist::stdev 30.673688
|
|
system.ruby.LD.latency_hist | 1093 92.39% 92.39% | 87 7.35% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.latency_hist::total 1183
|
|
system.ruby.LD.hit_latency_hist::bucket_size 2
|
|
system.ruby.LD.hit_latency_hist::max_bucket 19
|
|
system.ruby.LD.hit_latency_hist::samples 763
|
|
system.ruby.LD.hit_latency_hist::mean 3.376147
|
|
system.ruby.LD.hit_latency_hist::gmean 2.559264
|
|
system.ruby.LD.hit_latency_hist::stdev 3.447211
|
|
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.hit_latency_hist::total 763
|
|
system.ruby.LD.miss_latency_hist::bucket_size 64
|
|
system.ruby.LD.miss_latency_hist::max_bucket 639
|
|
system.ruby.LD.miss_latency_hist::samples 420
|
|
system.ruby.LD.miss_latency_hist::mean 57.942857
|
|
system.ruby.LD.miss_latency_hist::gmean 53.988115
|
|
system.ruby.LD.miss_latency_hist::stdev 26.600762
|
|
system.ruby.LD.miss_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.miss_latency_hist::total 420
|
|
system.ruby.ST.latency_hist::bucket_size 16
|
|
system.ruby.ST.latency_hist::max_bucket 159
|
|
system.ruby.ST.latency_hist::samples 865
|
|
system.ruby.ST.latency_hist::mean 11.732948
|
|
system.ruby.ST.latency_hist::gmean 3.862911
|
|
system.ruby.ST.latency_hist::stdev 20.767655
|
|
system.ruby.ST.latency_hist | 707 81.73% 81.73% | 41 4.74% 86.47% | 0 0.00% 86.47% | 78 9.02% 95.49% | 35 4.05% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.latency_hist::total 865
|
|
system.ruby.ST.hit_latency_hist::bucket_size 2
|
|
system.ruby.ST.hit_latency_hist::max_bucket 19
|
|
system.ruby.ST.hit_latency_hist::samples 707
|
|
system.ruby.ST.hit_latency_hist::mean 2.466761
|
|
system.ruby.ST.hit_latency_hist::gmean 2.174458
|
|
system.ruby.ST.hit_latency_hist::stdev 2.110935
|
|
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.hit_latency_hist::total 707
|
|
system.ruby.ST.miss_latency_hist::bucket_size 16
|
|
system.ruby.ST.miss_latency_hist::max_bucket 159
|
|
system.ruby.ST.miss_latency_hist::samples 158
|
|
system.ruby.ST.miss_latency_hist::mean 53.196203
|
|
system.ruby.ST.miss_latency_hist::gmean 50.539760
|
|
system.ruby.ST.miss_latency_hist::stdev 15.383612
|
|
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.miss_latency_hist::total 158
|
|
system.ruby.IFETCH.latency_hist::bucket_size 64
|
|
system.ruby.IFETCH.latency_hist::max_bucket 639
|
|
system.ruby.IFETCH.latency_hist::samples 6400
|
|
system.ruby.IFETCH.latency_hist::mean 7.853750
|
|
system.ruby.IFETCH.latency_hist::gmean 2.784724
|
|
system.ruby.IFETCH.latency_hist::stdev 20.410979
|
|
system.ruby.IFETCH.latency_hist | 6292 98.31% 98.31% | 99 1.55% 99.86% | 1 0.02% 99.88% | 0 0.00% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.latency_hist::total 6400
|
|
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
|
|
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
|
|
system.ruby.IFETCH.hit_latency_hist::samples 5819
|
|
system.ruby.IFETCH.hit_latency_hist::mean 2.111703
|
|
system.ruby.IFETCH.hit_latency_hist::gmean 2.040432
|
|
system.ruby.IFETCH.hit_latency_hist::stdev 1.051067
|
|
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.hit_latency_hist::total 5819
|
|
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
|
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
|
system.ruby.IFETCH.miss_latency_hist::samples 581
|
|
system.ruby.IFETCH.miss_latency_hist::mean 65.363167
|
|
system.ruby.IFETCH.miss_latency_hist::gmean 62.729888
|
|
system.ruby.IFETCH.miss_latency_hist::stdev 30.682702
|
|
system.ruby.IFETCH.miss_latency_hist | 473 81.41% 81.41% | 99 17.04% 98.45% | 1 0.17% 98.62% | 0 0.00% 98.62% | 4 0.69% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.miss_latency_hist::total 581
|
|
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
|
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
|
system.ruby.L1Cache.hit_mach_latency_hist::samples 7086
|
|
system.ruby.L1Cache.hit_mach_latency_hist::mean 2
|
|
system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000
|
|
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.L1Cache.hit_mach_latency_hist::total 7086
|
|
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 2
|
|
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 19
|
|
system.ruby.L2Cache.hit_mach_latency_hist::samples 203
|
|
system.ruby.L2Cache.hit_mach_latency_hist::mean 12
|
|
system.ruby.L2Cache.hit_mach_latency_hist::gmean 12.000000
|
|
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.L2Cache.hit_mach_latency_hist::total 203
|
|
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
|
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
|
system.ruby.Directory.miss_mach_latency_hist::samples 1159
|
|
system.ruby.Directory.miss_mach_latency_hist::mean 61.015531
|
|
system.ruby.Directory.miss_mach_latency_hist::gmean 57.685008
|
|
system.ruby.Directory.miss_mach_latency_hist::stdev 27.944488
|
|
system.ruby.Directory.miss_mach_latency_hist | 922 79.55% 79.55% | 225 19.41% 98.96% | 1 0.09% 99.05% | 0 0.00% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_mach_latency_hist::total 1159
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 75
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 75.000000
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 658
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 658
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 105
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 12
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 105
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 420
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.942857
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 53.988115
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.600762
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 674
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 674
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 33
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 12
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.196203
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.539760
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.383612
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 5754
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 2
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 5754
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 65
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 12
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 65
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.363167
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.729888
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 30.682702
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 473 81.41% 81.41% | 99 17.04% 98.45% | 1 0.17% 98.62% | 0 0.00% 98.62% | 4 0.69% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581
|
|
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
|
|
system.ruby.Directory_Controller.GETS 1020 0.00% 0.00%
|
|
system.ruby.Directory_Controller.PUT 1143 0.00% 0.00%
|
|
system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00%
|
|
system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00%
|
|
system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00%
|
|
system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00%
|
|
system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00%
|
|
system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00%
|
|
system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
|
|
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
|
|
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
|
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
|
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Store 892 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.L2_Replacement 1143 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.L1_to_L2 1354 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Exclusive_Data 1159 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Writeback_Ack 1143 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.All_acks_no_sharers 1159 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Load 420 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Load 304 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Ifetch 5754 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.L2_Replacement 923 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.L1_to_L2 1061 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM.Store 614 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM.L2_Replacement 220 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM.L1_to_L2 293 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 70 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MR.Load 62 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MR.Ifetch 65 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MR.Store 6 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1001 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.IS.Exclusive_Data 1001 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00%
|
|
|
|
---------- End Simulation Statistics ----------
|