8fe556338d
This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
767 lines
88 KiB
Plaintext
767 lines
88 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 12009000 # Number of ticks simulated
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final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 10920 # Simulator instruction rate (inst/s)
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host_op_rate 19780 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 24373770 # Simulator tick rate (ticks/s)
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host_mem_usage 225464 # Number of bytes of host memory used
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host_seconds 0.49 # Real time elapsed on the host
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sim_insts 5380 # Number of instructions simulated
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sim_ops 9745 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28800 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 450 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 451 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28800 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 11990500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 451 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 3096951 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests
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system.physmem.totBusLat 1804000 # Total cycles spent in databus access
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system.physmem.totBankLat 8540000 # Total cycles spent in bank access
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system.physmem.avgQLat 6866.85 # Average queueing delay per request
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system.physmem.avgBankLat 18935.70 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 29802.55 # Average memory access latency
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system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 14.99 # Data bus utilization in percentage
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system.physmem.avgRdQLen 1.12 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 353 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 26586.47 # Average gap between requests
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 24019 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 3185 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 3768 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 18260 # Type of FU issued
|
|
system.cpu.iq.rate 0.760231 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 195 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3340 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1687 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1410 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.716058 # Inst execution rate
|
|
system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 16726 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 10734 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 16630 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
|
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 1986 # Number of memory references committed
|
|
system.cpu.commit.loads 1052 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1208 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 36753 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 45519 # The number of ROB writes
|
|
system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
|
system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
|
system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 30259 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 18088 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 7500 # number of misc regfile reads
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1605 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1605 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 394 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1589 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1589 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2447 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2447 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2447 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2447 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 208 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2981000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6259500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6259500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6259500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6259500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040674 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040674 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.054991 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.054991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46835.714286 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46835.714286 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39223.684211 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39223.684211 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 182.959089 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 149.880234 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 33.078855 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004574 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001009 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005583 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 451 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10319000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3209500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 13528500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2905000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2905000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 10319000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6114500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 16433500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 10319000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6114500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 16433500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 306 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 306 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996732 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996732 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|