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gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson 8fe556338d stats: Update stats to reflect use of SimpleDRAM 
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.659992 # Number of seconds simulated
sim_ticks 659991928000 # Number of ticks simulated
final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 102750 # Simulator instruction rate (inst/s)
host_op_rate 139931 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48985343 # Simulator tick rate (ticks/s)
host_mem_usage 254632 # Number of bytes of host memory used
host_seconds 13473.25 # Real time elapsed on the host
sim_insts 1384374560 # Number of instructions simulated
sim_ops 1885329312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory
system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1479941 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 94716224 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 659991863500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 1479941 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 66098 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests
system.physmem.totBusLat 5902876000 # Total cycles spent in databus access
system.physmem.totBankLat 38831912000 # Total cycles spent in bank access
system.physmem.avgQLat 3793.07 # Average queueing delay per request
system.physmem.avgBankLat 26313.89 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 34106.96 # Average memory access latency
system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.94 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.08 # Average read queue length over time
system.physmem.avgWrQLen 14.18 # Average write queue length over time
system.physmem.readRowHits 809039 # Number of row buffer hits during reads
system.physmem.writeRowHits 36662 # Number of row buffer hits during writes
system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes
system.physmem.avgGap 426892.12 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1319983857 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed
system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued
system.cpu.iq.rate 1.882428 # Inst issue rate
system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 14409 # number of nop insts executed
system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed
system.cpu.iew.exec_branches 329779468 # Number of branches executed
system.cpu.iew.exec_stores 441837188 # Number of stores executed
system.cpu.iew.exec_rate 1.822772 # Inst execution rate
system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1358943525 # num instructions producing a value
system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384385576 # Number of instructions committed
system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908384066 # Number of memory references committed
system.cpu.commit.loads 631387975 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 299635189 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3905904114 # The number of ROB reads
system.cpu.rob.rob_writes 5865307964 # The number of ROB writes
system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384374560 # Number of Instructions Simulated
system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated
system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads
system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads
system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes
system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads
system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes
system.cpu.misc_regfile_reads 3727888158 # number of misc regfile reads
system.cpu.misc_regfile_writes 13774490 # number of misc regfile writes
system.cpu.icache.replacements 23076 # number of replacements
system.cpu.icache.tagsinuse 1653.132974 # Cycle average of tags in use
system.cpu.icache.total_refs 352429997 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 24765 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14230.971007 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1653.132974 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.807194 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.807194 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 352434103 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 352434103 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 352434103 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 352434103 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 352434103 # number of overall hits
system.cpu.icache.overall_hits::total 352434103 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 29669 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 29669 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 29669 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 29669 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 29669 # number of overall misses
system.cpu.icache.overall_misses::total 29669 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 256567500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 256567500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 256567500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 256567500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 256567500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 256567500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 352463772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 352463772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 352463772 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 352463772 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 352463772 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 352463772 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8647.662543 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8647.662543 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8647.662543 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8647.662543 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 738 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 738 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 738 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 738 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 738 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 738 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28931 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 28931 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 28931 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 28931 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 28931 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 28931 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178433000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 178433000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178433000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 178433000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178433000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 178433000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6167.536552 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6167.536552 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1533235 # number of replacements
system.cpu.dcache.tagsinuse 4094.869938 # Cycle average of tags in use
system.cpu.dcache.total_refs 976399177 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1537331 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 635.126188 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 278705000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.869938 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999724 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999724 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 700249991 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 700249991 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 276118441 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11312 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11312 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::total 10779 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::total 976368432 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::total 976368432 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 2072491 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 817237 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 10 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 10 # number of LoadLockedReq misses
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system.cpu.dcache.demand_misses::total 2889728 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 2889728 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 84515499000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 31029320000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 296000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 115544819000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 115544819000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 115544819000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 702322482 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 11322 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10779 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10779 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 979258160 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 979258160 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.002951 # miss rate for WriteReq accesses
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system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000883 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.002951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40779.669972 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40779.669972 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37968.569705 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37968.569705 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29600 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29600 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39984.669491 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39984.669491 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::total 108671 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 607721 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 740509 # number of WriteReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_hits::total 10 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1348230 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 1348230 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 1464770 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 76728 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 1541498 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 1541498 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 56538138500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 2635948000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 59174086500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 59174086500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002086 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.001574 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.001574 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38598.645862 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34354.446877 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34354.446877 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480138 # number of replacements
system.cpu.l2cache.tagsinuse 32697.181297 # Cycle average of tags in use
system.cpu.l2cache.total_refs 84298 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512881 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.055720 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 3151.564148 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 56.407826 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 29489.209323 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.096178 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001721 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.899939 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.data 53983 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 75635 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::total 108671 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::total 6484 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 60467 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 60467 # number of overall hits
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system.cpu.l2cache.UpgradeReq_misses::total 4164 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66079 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66079 # number of ReadExReq misses
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system.cpu.l2cache.overall_misses::cpu.data 1476864 # number of overall misses
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system.cpu.l2cache.overall_miss_latency::cpu.data 57555270000 # number of overall miss cycles
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system.cpu.l2cache.Writeback_accesses::writebacks 108671 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 108671 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38998.523871 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38389.465640 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38971.272913 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 38972.650588 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 39626.244780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38971.272913 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38972.650588 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits::cpu.data 25 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 36 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52043294256 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963129 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910643 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910643 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.125257 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960651 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.947407 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.125257 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960651 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.947407 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.827531 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35275.227637 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35277.085069 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34480.154285 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34480.154285 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36121.827531 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35239.653243 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35241.502307 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36121.827531 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35239.653243 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35241.502307 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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