gem5/python/m5/objects
Ali Saidi 8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00
..
AlphaConsole.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
AlphaFullCPU.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
AlphaTLB.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
BadDevice.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
BaseCache.py Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
BaseCPU.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Bus.py Implement a very very simple bus 2006-03-25 18:31:20 -05:00
CoherenceProtocol.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Device.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
DiskImage.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Ethernet.py Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
Ide.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
IntrControl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
MemObject.py Update functional memory to have a response event 2006-02-23 13:51:54 -05:00
MemTest.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Pci.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
PhysicalMemory.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
Platform.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Process.py add translations for new sections that are mmapped or when the brk 2006-03-15 17:04:50 -05:00
Repl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Root.py More progress toward actually running a program. 2006-03-01 18:45:50 -05:00
SimConsole.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
SimpleDisk.py fixes for newmem 2006-04-06 14:57:51 -04:00
System.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Tsunami.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Uart.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00