gem5/configs/common/Caches.py
Andreas Hansson fbdeb60316 mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.

The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
2016-02-10 04:08:24 -05:00

94 lines
3.4 KiB
Python

# Copyright (c) 2012 ARM Limited
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#
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# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
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# modification, are permitted provided that the following conditions are
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# this software without specific prior written permission.
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu
from m5.objects import *
# Base implementations of L1, L2, IO and TLB-walker caches. There are
# used in the regressions and also as base components in the
# system-configuration scripts. The values are meant to serve as a
# starting point, and specific parameters can be overridden in the
# specific instantiations.
class L1Cache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
class L1_ICache(L1Cache):
is_read_only = True
# Writeback clean lines as well
writeback_clean = True
class L1_DCache(L1Cache):
pass
class L2Cache(Cache):
assoc = 8
hit_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12
write_buffers = 8
class IOCache(Cache):
assoc = 8
hit_latency = 50
response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
class PageTableWalkerCache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] == 'x86':
is_read_only = False
else:
is_read_only = True
# Writeback clean lines as well
writeback_clean = True