1195 lines
137 KiB
Text
1195 lines
137 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.058182 # Number of seconds simulated
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sim_ticks 58182114500 # Number of ticks simulated
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final_tick 58182114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 128679 # Simulator instruction rate (inst/s)
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host_op_rate 129320 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 82645168 # Simulator tick rate (ticks/s)
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host_mem_usage 446228 # Number of bytes of host memory used
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host_seconds 704.00 # Real time elapsed on the host
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sim_insts 90589799 # Number of instructions simulated
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sim_ops 91041030 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 44288 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 51456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 933184 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1028928 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 44288 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 44288 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 27456 # Number of bytes written to this memory
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system.physmem.bytes_written::total 27456 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 692 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 804 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 14581 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 16077 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 429 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 429 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 761196 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 884395 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 16039018 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 17684610 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 761196 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 761196 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 471898 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 471898 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 471898 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 761196 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 884395 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 16039018 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 18156508 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 16077 # Number of read requests accepted
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system.physmem.writeReqs 429 # Number of write requests accepted
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system.physmem.readBursts 16077 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 429 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 1014080 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 14848 # Total number of bytes read from write queue
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system.physmem.bytesWritten 26048 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 1028928 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 27456 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 232 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 1011 # Per bank write bursts
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system.physmem.perBankRdBursts::1 876 # Per bank write bursts
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system.physmem.perBankRdBursts::2 957 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1029 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1060 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1137 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1146 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1099 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1049 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 940 # Per bank write bursts
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system.physmem.perBankRdBursts::11 901 # Per bank write bursts
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system.physmem.perBankRdBursts::12 907 # Per bank write bursts
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system.physmem.perBankRdBursts::13 888 # Per bank write bursts
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system.physmem.perBankRdBursts::14 960 # Per bank write bursts
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system.physmem.perBankRdBursts::15 923 # Per bank write bursts
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system.physmem.perBankWrBursts::0 29 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4 # Per bank write bursts
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system.physmem.perBankWrBursts::5 30 # Per bank write bursts
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system.physmem.perBankWrBursts::6 102 # Per bank write bursts
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system.physmem.perBankWrBursts::7 27 # Per bank write bursts
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system.physmem.perBankWrBursts::8 34 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 11 # Per bank write bursts
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system.physmem.perBankWrBursts::11 5 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6 # Per bank write bursts
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system.physmem.perBankWrBursts::13 38 # Per bank write bursts
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system.physmem.perBankWrBursts::14 82 # Per bank write bursts
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system.physmem.perBankWrBursts::15 24 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 58181957500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 16077 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 429 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 10965 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 454 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 298 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1937 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 535.822406 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 300.454496 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 434.844935 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 623 32.16% 32.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 199 10.27% 42.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 99 5.11% 47.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 70 3.61% 51.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 49 2.53% 53.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 51 2.63% 56.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 51 2.63% 58.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 47 2.43% 61.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 748 38.62% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1937 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 687.695652 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 31.373989 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 3139.186163 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.695652 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.676543 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.822125 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 4 17.39% 17.39% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 18 78.26% 95.65% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1 4.35% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads
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system.physmem.totQLat 162696744 # Total ticks spent queuing
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system.physmem.totMemAccLat 459790494 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 79225000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10268.02 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29018.02 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.45 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 17.68 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.47 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.14 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 18.75 # Average write queue length when enqueuing
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system.physmem.readRowHits 14165 # Number of row buffer hits during reads
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system.physmem.writeRowHits 138 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 32.47 # Row buffer hit rate for writes
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system.physmem.avgGap 3524897.46 # Average gap between requests
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system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 7749000 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 4228125 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 64591800 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 1302480 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2489657400 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 32723562000 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 39091051125 # Total energy per rank (pJ)
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system.physmem_0.averagePower 671.908601 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 54427806081 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1808607669 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 6811560 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 3716625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 58687200 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 1211760 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 2472306885 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 32738773500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 39081467850 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 671.744040 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 54453180249 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 1783438751 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 28257673 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 23279792 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 837861 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11842586 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 11784928 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.513130 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 75759 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
|
system.cpu.numCycles 116364230 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 748840 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 134987137 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 28257673 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 11860687 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 114722877 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 32301983 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 116313064 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.165803 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.319035 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 58742008 50.50% 50.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 13941997 11.99% 62.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 9231022 7.94% 70.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 34398037 29.57% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 116313064 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.160040 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8839881 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 64052748 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 33035096 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9558012 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 4101304 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 114430189 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 1996961 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 15280915 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 49896712 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 109420 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 35425336 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 14773354 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 110898724 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 1415582 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 11131047 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1144428 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1527040 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 487812 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 483272365 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 119474128 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 21506605 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 26812984 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5349507 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 517744 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 254125 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 109690412 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 101387626 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1074735 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 18657629 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 41690294 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 116313064 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.871679 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 0.989298 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 54672209 47.00% 47.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 31362113 26.96% 73.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 22008866 18.92% 92.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7072036 6.08% 98.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1197527 1.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 116313064 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9793385 48.69% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 14 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 9616432 47.81% 96.50% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 703828 3.50% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 71984128 71.00% 71.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 24343025 24.01% 95.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5049584 4.98% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 101387626 # Type of FU issued
|
|
system.cpu.iq.rate 0.871295 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 20113709 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.198384 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 340276307 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 128356979 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 99625202 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 121501099 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 290480 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4337073 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1343 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 604663 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7562 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 130598 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 8118752 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 684481 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 109711326 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 26812984 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5349507 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 179113 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 342349 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1343 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 436660 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 849532 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 100126680 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 23806374 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1260946 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12667 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 28724279 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 20624229 # Number of branches executed
|
|
system.cpu.iew.exec_stores 4917905 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.860459 # Inst execution rate
|
|
system.cpu.iew.wb_sent 99709898 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 99625314 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 59703303 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 95544285 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.856151 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 17385621 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 825623 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 113620717 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.801382 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.737978 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 77197638 67.94% 67.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 18614899 16.38% 84.33% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 7150727 6.29% 90.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3466583 3.05% 93.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1641577 1.44% 95.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 544810 0.48% 95.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 704355 0.62% 96.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 179975 0.16% 96.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 4120153 3.63% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 113620717 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90602408 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27220755 # Number of memory references committed
|
|
system.cpu.commit.loads 22475911 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18732305 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 4120153 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 217934090 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 219571457 # The number of ROB writes
|
|
system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 51166 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90589799 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.284518 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.284518 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.778502 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.778502 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 108111423 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 58700979 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 92 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 369063033 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 58693305 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 28414934 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 5470204 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.787652 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 18251843 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 5470716 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 3.336280 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.787652 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 61908596 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 61908596 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13889769 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13889769 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4353793 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4353793 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 18243562 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 18243562 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 18244084 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 18244084 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 9585887 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 9585887 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 381188 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 381188 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9967075 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9967075 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9967082 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9967082 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721516500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 88721516500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4007000296 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4007000296 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 92728516796 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 92728516796 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 92728516796 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 92728516796 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23475656 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23475656 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 28210637 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 28210637 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 28211166 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 28211166 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408333 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.408333 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080505 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.080505 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.353309 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.353309 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.353303 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.353303 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.431083 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.431083 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.483399 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 9303.483399 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.476865 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 9303.476865 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 329940 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 111027 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 121461 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716427 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 8.648310 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 5432438 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 5432438 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337660 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 4337660 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158703 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 158703 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4496363 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4496363 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4496363 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4496363 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248227 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 5248227 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 5470712 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 5470712 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 5470716 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 5470716 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43248007500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43248007500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2284927222 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2284927222 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532934722 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 45532934722 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45533149222 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 45533149222 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193924 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.193924 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.498648 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.498648 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.036329 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.036329 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.069452 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.069452 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 451 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 428.507566 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 32300812 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 35495.397802 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 428.507566 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 64604850 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 64604850 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 32300812 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 32300812 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 32300812 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 32300812 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 32300812 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 32300812 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1158 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61588984 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 61588984 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 61588984 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 61588984 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 61588984 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 61588984 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 32301970 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 32301970 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 32301970 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 32301970 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 32301970 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 32301970 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 53185.651123 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 53185.651123 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 19024 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 84.551111 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49864488 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 49864488 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49864488 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 49864488 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49864488 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 49864488 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54796.140659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54796.140659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 4982376 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 5297288 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 273784 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 14074296 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 642 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 12072.124687 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 10689018 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 16082 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 664.657257 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 574.634156 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 222.368326 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 216.541992 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.674962 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035073 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.013572 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013217 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.736824 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15165 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 238 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1062 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.925598 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 175272448 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 175272448 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 5432438 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 5432438 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 226006 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 226006 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 217 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 217 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243653 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 5243653 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 217 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 5469659 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 5469876 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 217 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 5469659 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 5469876 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 504 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 504 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 693 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 693 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 553 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 553 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 693 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1057 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1750 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 693 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1057 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1750 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42131500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 42131500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47516500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47516500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32807500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 32807500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 47516500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 74939000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 122455500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 47516500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 74939000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 122455500 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 5432438 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 5432438 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 226510 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 226510 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 910 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 910 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244206 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 5244206 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 5470716 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 5471626 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 5470716 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 5471626 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002225 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002225 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.761538 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.761538 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000105 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000105 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.761538 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.000320 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.761538 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.000320 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83594.246032 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83594.246032 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68566.378066 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68566.378066 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59326.401447 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59326.401447 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68566.378066 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70897.824030 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69974.571429 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68566.378066 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70897.824030 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69974.571429 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 429 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 429 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 163 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 163 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 90 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 90 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 253 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 253 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 254 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 13 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 13 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20697 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 20697 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 692 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 692 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 463 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 463 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 692 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 804 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1496 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 692 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 804 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20697 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 22193 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 848986877 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 848986877 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32854500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32854500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43305000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43305000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25953500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25953500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43305000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58808000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 102113000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43305000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58808000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 848986877 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 951099877 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.760440 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.760440 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000088 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.760440 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000147 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000273 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.760440 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000147 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.004056 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5245116 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 5432867 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 35515 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 22583 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 226510 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 226510 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244206 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408733 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 16410992 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697801856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 697860096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 23225 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 10965506 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.002118 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.045973 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 10942281 99.79% 99.79% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 23225 0.21% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 10965506 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10903578500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 8206077992 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 15736 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 429 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 169 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 341 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 341 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 15736 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32752 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 32752 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056384 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 1056384 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 16675 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 16675 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 16675 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 28309413 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 84107303 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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