1728 lines
46 KiB
C++
1728 lines
46 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cstdio>
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#include <deque>
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#include <string>
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#include "base/inet.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/intr_control.hh"
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#include "dev/etherlink.hh"
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#include "dev/sinic.hh"
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#include "dev/pciconfigall.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/dma_interface.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/eventq.hh"
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#include "sim/host.hh"
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#include "sim/stats.hh"
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#include "arch/vtophys.hh"
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using namespace Net;
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using namespace TheISA;
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namespace Sinic {
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const char *RxStateStrings[] =
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{
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"rxIdle",
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"rxFifoBlock",
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"rxBeginCopy",
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"rxCopy",
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"rxCopyDone"
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};
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const char *TxStateStrings[] =
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{
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"txIdle",
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"txFifoBlock",
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"txBeginCopy",
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"txCopy",
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"txCopyDone"
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};
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///////////////////////////////////////////////////////////////////////
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//
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// Sinic PCI Device
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//
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Base::Base(Params *p)
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: PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
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intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
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cpuPendingIntr(false), intrEvent(0), interface(NULL)
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{
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}
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Device::Device(Params *p)
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: Base(p), plat(p->plat), physmem(p->physmem),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
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rxKickTick(0), txKickTick(0),
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txEvent(this), rxDmaEvent(this), txDmaEvent(this),
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dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
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dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
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{
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reset();
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if (p->pio_bus) {
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pioInterface = newPioInterface(p->name + ".pio", p->hier, p->pio_bus,
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this, &Device::cacheAccess);
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pioLatency = p->pio_latency * p->pio_bus->clockRate;
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}
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if (p->header_bus) {
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if (p->payload_bus)
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dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
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p->header_bus,
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p->payload_bus, 1,
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p->dma_no_allocate);
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else
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dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
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p->header_bus,
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p->header_bus, 1,
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p->dma_no_allocate);
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} else if (p->payload_bus)
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panic("must define a header bus if defining a payload bus");
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}
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Device::~Device()
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{}
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void
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Device::regStats()
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{
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rxBytes
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.name(name() + ".rxBytes")
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.desc("Bytes Received")
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.prereq(rxBytes)
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;
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rxBandwidth
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.name(name() + ".rxBandwidth")
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.desc("Receive Bandwidth (bits/s)")
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.precision(0)
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.prereq(rxBytes)
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;
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rxPackets
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.name(name() + ".rxPackets")
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.desc("Number of Packets Received")
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.prereq(rxBytes)
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;
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rxPacketRate
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.name(name() + ".rxPPS")
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.desc("Packet Reception Rate (packets/s)")
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.precision(0)
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.prereq(rxBytes)
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;
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rxIpPackets
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.name(name() + ".rxIpPackets")
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.desc("Number of IP Packets Received")
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.prereq(rxBytes)
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;
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rxTcpPackets
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.name(name() + ".rxTcpPackets")
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.desc("Number of Packets Received")
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.prereq(rxBytes)
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;
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rxUdpPackets
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.name(name() + ".rxUdpPackets")
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.desc("Number of UDP Packets Received")
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.prereq(rxBytes)
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;
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rxIpChecksums
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.name(name() + ".rxIpChecksums")
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.desc("Number of rx IP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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rxTcpChecksums
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.name(name() + ".rxTcpChecksums")
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.desc("Number of rx TCP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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rxUdpChecksums
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.name(name() + ".rxUdpChecksums")
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.desc("Number of rx UDP Checksums done by device")
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.precision(0)
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.prereq(rxBytes)
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;
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totBandwidth
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.name(name() + ".totBandwidth")
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.desc("Total Bandwidth (bits/s)")
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.precision(0)
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.prereq(totBytes)
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;
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totPackets
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.name(name() + ".totPackets")
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.desc("Total Packets")
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.precision(0)
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.prereq(totBytes)
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;
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totBytes
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.name(name() + ".totBytes")
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.desc("Total Bytes")
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.precision(0)
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.prereq(totBytes)
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;
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totPacketRate
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.name(name() + ".totPPS")
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.desc("Total Tranmission Rate (packets/s)")
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.precision(0)
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.prereq(totBytes)
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;
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txBytes
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.name(name() + ".txBytes")
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.desc("Bytes Transmitted")
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.prereq(txBytes)
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;
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txBandwidth
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.name(name() + ".txBandwidth")
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.desc("Transmit Bandwidth (bits/s)")
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.precision(0)
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.prereq(txBytes)
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;
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txPackets
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.name(name() + ".txPackets")
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.desc("Number of Packets Transmitted")
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.prereq(txBytes)
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;
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txPacketRate
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.name(name() + ".txPPS")
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.desc("Packet Tranmission Rate (packets/s)")
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.precision(0)
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.prereq(txBytes)
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;
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txIpPackets
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.name(name() + ".txIpPackets")
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.desc("Number of IP Packets Transmitted")
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.prereq(txBytes)
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;
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txTcpPackets
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.name(name() + ".txTcpPackets")
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.desc("Number of TCP Packets Transmitted")
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.prereq(txBytes)
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;
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txUdpPackets
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.name(name() + ".txUdpPackets")
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.desc("Number of Packets Transmitted")
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.prereq(txBytes)
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;
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txIpChecksums
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.name(name() + ".txIpChecksums")
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.desc("Number of tx IP Checksums done by device")
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.precision(0)
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.prereq(txBytes)
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;
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txTcpChecksums
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.name(name() + ".txTcpChecksums")
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.desc("Number of tx TCP Checksums done by device")
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.precision(0)
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.prereq(txBytes)
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;
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txUdpChecksums
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.name(name() + ".txUdpChecksums")
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.desc("Number of tx UDP Checksums done by device")
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.precision(0)
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.prereq(txBytes)
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;
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txBandwidth = txBytes * Stats::constant(8) / simSeconds;
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rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
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totBandwidth = txBandwidth + rxBandwidth;
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totBytes = txBytes + rxBytes;
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totPackets = txPackets + rxPackets;
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txPacketRate = txPackets / simSeconds;
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rxPacketRate = rxPackets / simSeconds;
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}
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/**
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* This is to write to the PCI general configuration registers
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*/
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void
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Device::writeConfig(int offset, int size, const uint8_t *data)
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{
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switch (offset) {
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case PCI0_BASE_ADDR0:
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// Need to catch writes to BARs to update the PIO interface
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PciDev::writeConfig(offset, size, data);
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if (BARAddrs[0] != 0) {
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if (pioInterface)
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pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
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BARAddrs[0] &= EV5::PAddrUncachedMask;
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}
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break;
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default:
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PciDev::writeConfig(offset, size, data);
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}
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}
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void
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Device::prepareIO(int cpu, int index)
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{
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int size = virtualRegs.size();
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if (index < size)
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return;
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virtualRegs.resize(index + 1);
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for (int i = size; i <= index; ++i)
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virtualRegs[i].rxPacket = rxFifo.end();
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}
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void
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Device::prepareRead(int cpu, int index)
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{
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using namespace Regs;
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prepareIO(cpu, index);
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VirtualReg &vnic = virtualRegs[index];
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// update rx registers
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uint64_t rxdone = vnic.RxDone;
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rxdone = set_RxDone_Packets(rxdone, rxFifo.packets());
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regs.RxData = vnic.RxData;
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regs.RxDone = rxdone;
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regs.RxWait = rxdone;
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// update tx regsiters
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uint64_t txdone = vnic.TxDone;
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txdone = set_TxDone_Packets(txdone, txFifo.packets());
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txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy);
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txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoMark);
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regs.TxData = vnic.TxData;
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regs.TxDone = txdone;
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regs.TxWait = txdone;
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}
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void
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Device::prepareWrite(int cpu, int index)
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{
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prepareIO(cpu, index);
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}
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/**
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* I/O read of device register
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*/
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Fault
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Device::read(MemReqPtr &req, uint8_t *data)
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{
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assert(config.command & PCI_CMD_MSE);
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Fault fault = readBar(req, data);
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if (fault->isMachineCheckFault()) {
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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req->paddr, req->vaddr, req->size);
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return genMachineCheckFault();
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}
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return fault;
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}
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Fault
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Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
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{
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int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
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Addr index = daddr >> Regs::VirtualShift;
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Addr raddr = daddr & Regs::VirtualMask;
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if (!regValid(raddr))
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panic("invalid register: cpu=%d, da=%#x pa=%#x va=%#x size=%d",
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cpu, daddr, req->paddr, req->vaddr, req->size);
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const Regs::Info &info = regInfo(raddr);
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if (!info.read)
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panic("reading %s (write only): cpu=%d da=%#x pa=%#x va=%#x size=%d",
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info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
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if (req->size != info.size)
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panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
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info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
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prepareRead(cpu, index);
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uint64_t value = 0;
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if (req->size == 4) {
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uint32_t ® = *(uint32_t *)data;
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reg = regData32(raddr);
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value = reg;
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}
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if (req->size == 8) {
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uint64_t ® = *(uint64_t *)data;
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reg = regData64(raddr);
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value = reg;
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}
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DPRINTF(EthernetPIO,
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"read %s cpu=%d da=%#x pa=%#x va=%#x size=%d val=%#x\n",
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info.name, cpu, daddr, req->paddr, req->vaddr, req->size, value);
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// reading the interrupt status register has the side effect of
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// clearing it
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if (raddr == Regs::IntrStatus)
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devIntrClear();
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return NoFault;
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}
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/**
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* IPR read of device register
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*/
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Fault
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Device::iprRead(Addr daddr, int cpu, uint64_t &result)
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{
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if (!regValid(daddr))
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panic("invalid address: da=%#x", daddr);
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const Regs::Info &info = regInfo(daddr);
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if (!info.read)
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panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);
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DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n",
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info.name, cpu, daddr);
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prepareRead(cpu, 0);
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if (info.size == 4)
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result = regData32(daddr);
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if (info.size == 8)
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result = regData64(daddr);
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DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
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info.name, cpu, result);
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return NoFault;
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}
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/**
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* I/O write of device register
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*/
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Fault
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Device::write(MemReqPtr &req, const uint8_t *data)
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{
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assert(config.command & PCI_CMD_MSE);
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Fault fault = writeBar(req, data);
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if (fault->isMachineCheckFault()) {
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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req->paddr, req->vaddr, req->size);
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return genMachineCheckFault();
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}
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return fault;
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}
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|
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Fault
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Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{
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int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
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Addr index = daddr >> Regs::VirtualShift;
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Addr raddr = daddr & Regs::VirtualMask;
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if (!regValid(raddr))
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panic("invalid address: cpu=%d da=%#x pa=%#x va=%#x size=%d",
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cpu, daddr, req->paddr, req->vaddr, req->size);
|
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const Regs::Info &info = regInfo(raddr);
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if (!info.write)
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panic("writing %s (read only): cpu=%d da=%#x",
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info.name, cpu, daddr);
|
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if (req->size != info.size)
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panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
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info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
|
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|
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//These are commmented out because when the DPRINTF below isn't used,
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//these values aren't used and gcc issues a warning. With -Werror,
|
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//this prevents compilation.
|
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//uint32_t reg32 = *(uint32_t *)data;
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//uint64_t reg64 = *(uint64_t *)data;
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VirtualReg &vnic = virtualRegs[index];
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DPRINTF(EthernetPIO,
|
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"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
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info.name, cpu, info.size == 4 ?
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(*(uint32_t *)data) :
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(*(uint64_t *)data),
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daddr, req->paddr, req->vaddr, req->size);
|
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|
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prepareWrite(cpu, index);
|
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|
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switch (raddr) {
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case Regs::Config:
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changeConfig(reg32);
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break;
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|
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case Regs::Command:
|
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command(reg32);
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break;
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|
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case Regs::IntrStatus:
|
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devIntrClear(regs.IntrStatus & reg32);
|
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break;
|
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|
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case Regs::IntrMask:
|
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devIntrChangeMask(reg32);
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break;
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|
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case Regs::RxData:
|
|
if (Regs::get_RxDone_Busy(vnic.RxDone))
|
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panic("receive machine busy with another request! rxState=%s",
|
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RxStateStrings[rxState]);
|
|
|
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vnic.RxDone = Regs::RxDone_Busy;
|
|
vnic.RxData = reg64;
|
|
rxList.push_back(index);
|
|
if (rxEnable && rxState == rxIdle) {
|
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rxState = rxFifoBlock;
|
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rxKick();
|
|
}
|
|
break;
|
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|
|
case Regs::TxData:
|
|
if (Regs::get_TxDone_Busy(vnic.TxDone))
|
|
panic("transmit machine busy with another request! txState=%s",
|
|
TxStateStrings[txState]);
|
|
|
|
vnic.TxDone = Regs::TxDone_Busy;
|
|
vnic.TxData = reg64;
|
|
if (txList.empty() || txList.front() != index)
|
|
txList.push_back(index);
|
|
if (txEnable && txState == txIdle && txList.front() == index) {
|
|
txState = txFifoBlock;
|
|
txKick();
|
|
}
|
|
break;
|
|
}
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
void
|
|
Device::devIntrPost(uint32_t interrupts)
|
|
{
|
|
if ((interrupts & Regs::Intr_Res))
|
|
panic("Cannot set a reserved interrupt");
|
|
|
|
regs.IntrStatus |= interrupts;
|
|
|
|
DPRINTF(EthernetIntr,
|
|
"interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
|
|
interrupts, regs.IntrStatus, regs.IntrMask);
|
|
|
|
interrupts = regs.IntrStatus & regs.IntrMask;
|
|
|
|
// Intr_RxHigh is special, we only signal it if we've emptied the fifo
|
|
// and then filled it above the high watermark
|
|
if (rxEmpty)
|
|
rxEmpty = false;
|
|
else
|
|
interrupts &= ~Regs::Intr_RxHigh;
|
|
|
|
// Intr_TxLow is special, we only signal it if we've filled up the fifo
|
|
// and then dropped below the low watermark
|
|
if (txFull)
|
|
txFull = false;
|
|
else
|
|
interrupts &= ~Regs::Intr_TxLow;
|
|
|
|
if (interrupts) {
|
|
Tick when = curTick;
|
|
if ((interrupts & Regs::Intr_NoDelay) == 0)
|
|
when += intrDelay;
|
|
cpuIntrPost(when);
|
|
}
|
|
}
|
|
|
|
void
|
|
Device::devIntrClear(uint32_t interrupts)
|
|
{
|
|
if ((interrupts & Regs::Intr_Res))
|
|
panic("Cannot clear a reserved interrupt");
|
|
|
|
regs.IntrStatus &= ~interrupts;
|
|
|
|
DPRINTF(EthernetIntr,
|
|
"interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
|
|
interrupts, regs.IntrStatus, regs.IntrMask);
|
|
|
|
if (!(regs.IntrStatus & regs.IntrMask))
|
|
cpuIntrClear();
|
|
}
|
|
|
|
void
|
|
Device::devIntrChangeMask(uint32_t newmask)
|
|
{
|
|
if (regs.IntrMask == newmask)
|
|
return;
|
|
|
|
regs.IntrMask = newmask;
|
|
|
|
DPRINTF(EthernetIntr,
|
|
"interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
|
|
regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
|
|
|
|
if (regs.IntrStatus & regs.IntrMask)
|
|
cpuIntrPost(curTick);
|
|
else
|
|
cpuIntrClear();
|
|
}
|
|
|
|
void
|
|
Base::cpuIntrPost(Tick when)
|
|
{
|
|
// If the interrupt you want to post is later than an interrupt
|
|
// already scheduled, just let it post in the coming one and don't
|
|
// schedule another.
|
|
// HOWEVER, must be sure that the scheduled intrTick is in the
|
|
// future (this was formerly the source of a bug)
|
|
/**
|
|
* @todo this warning should be removed and the intrTick code should
|
|
* be fixed.
|
|
*/
|
|
assert(when >= curTick);
|
|
assert(intrTick >= curTick || intrTick == 0);
|
|
if (!cpuIntrEnable) {
|
|
DPRINTF(EthernetIntr, "interrupts not enabled.\n",
|
|
intrTick);
|
|
return;
|
|
}
|
|
|
|
if (when > intrTick && intrTick != 0) {
|
|
DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
|
|
intrTick);
|
|
return;
|
|
}
|
|
|
|
intrTick = when;
|
|
if (intrTick < curTick) {
|
|
debug_break();
|
|
intrTick = curTick;
|
|
}
|
|
|
|
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
|
|
intrTick);
|
|
|
|
if (intrEvent)
|
|
intrEvent->squash();
|
|
intrEvent = new IntrEvent(this, true);
|
|
intrEvent->schedule(intrTick);
|
|
}
|
|
|
|
void
|
|
Base::cpuInterrupt()
|
|
{
|
|
assert(intrTick == curTick);
|
|
|
|
// Whether or not there's a pending interrupt, we don't care about
|
|
// it anymore
|
|
intrEvent = 0;
|
|
intrTick = 0;
|
|
|
|
// Don't send an interrupt if there's already one
|
|
if (cpuPendingIntr) {
|
|
DPRINTF(EthernetIntr,
|
|
"would send an interrupt now, but there's already pending\n");
|
|
} else {
|
|
// Send interrupt
|
|
cpuPendingIntr = true;
|
|
|
|
DPRINTF(EthernetIntr, "posting interrupt\n");
|
|
intrPost();
|
|
}
|
|
}
|
|
|
|
void
|
|
Base::cpuIntrClear()
|
|
{
|
|
if (!cpuPendingIntr)
|
|
return;
|
|
|
|
if (intrEvent) {
|
|
intrEvent->squash();
|
|
intrEvent = 0;
|
|
}
|
|
|
|
intrTick = 0;
|
|
|
|
cpuPendingIntr = false;
|
|
|
|
DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
|
|
intrClear();
|
|
}
|
|
|
|
bool
|
|
Base::cpuIntrPending() const
|
|
{ return cpuPendingIntr; }
|
|
|
|
void
|
|
Device::changeConfig(uint32_t newconf)
|
|
{
|
|
uint32_t changed = regs.Config ^ newconf;
|
|
if (!changed)
|
|
return;
|
|
|
|
regs.Config = newconf;
|
|
|
|
if ((changed & Regs::Config_IntEn)) {
|
|
cpuIntrEnable = regs.Config & Regs::Config_IntEn;
|
|
if (cpuIntrEnable) {
|
|
if (regs.IntrStatus & regs.IntrMask)
|
|
cpuIntrPost(curTick);
|
|
} else {
|
|
cpuIntrClear();
|
|
}
|
|
}
|
|
|
|
if ((changed & Regs::Config_TxEn)) {
|
|
txEnable = regs.Config & Regs::Config_TxEn;
|
|
if (txEnable)
|
|
txKick();
|
|
}
|
|
|
|
if ((changed & Regs::Config_RxEn)) {
|
|
rxEnable = regs.Config & Regs::Config_RxEn;
|
|
if (rxEnable)
|
|
rxKick();
|
|
}
|
|
}
|
|
|
|
void
|
|
Device::command(uint32_t command)
|
|
{
|
|
if (command & Regs::Command_Intr)
|
|
devIntrPost(Regs::Intr_Soft);
|
|
|
|
if (command & Regs::Command_Reset)
|
|
reset();
|
|
}
|
|
|
|
void
|
|
Device::reset()
|
|
{
|
|
using namespace Regs;
|
|
|
|
memset(®s, 0, sizeof(regs));
|
|
|
|
regs.Config = 0;
|
|
if (params()->rx_thread)
|
|
regs.Config |= Config_RxThread;
|
|
if (params()->tx_thread)
|
|
regs.Config |= Config_TxThread;
|
|
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
|
|
regs.RxMaxCopy = params()->rx_max_copy;
|
|
regs.TxMaxCopy = params()->tx_max_copy;
|
|
regs.RxMaxIntr = params()->rx_max_intr;
|
|
regs.RxFifoSize = params()->rx_fifo_size;
|
|
regs.TxFifoSize = params()->tx_fifo_size;
|
|
regs.RxFifoMark = params()->rx_fifo_threshold;
|
|
regs.TxFifoMark = params()->tx_fifo_threshold;
|
|
regs.HwAddr = params()->eaddr;
|
|
|
|
rxList.clear();
|
|
txList.clear();
|
|
|
|
rxState = rxIdle;
|
|
txState = txIdle;
|
|
|
|
rxFifo.clear();
|
|
rxFifoPtr = rxFifo.end();
|
|
txFifo.clear();
|
|
rxEmpty = false;
|
|
txFull = false;
|
|
|
|
int size = virtualRegs.size();
|
|
virtualRegs.clear();
|
|
virtualRegs.resize(size);
|
|
for (int i = 0; i < size; ++i)
|
|
virtualRegs[i].rxPacket = rxFifo.end();
|
|
}
|
|
|
|
void
|
|
Device::rxDmaCopy()
|
|
{
|
|
assert(rxState == rxCopy);
|
|
rxState = rxCopyDone;
|
|
physmem->dma_write(rxDmaAddr, (uint8_t *)rxDmaData, rxDmaLen);
|
|
DPRINTF(EthernetDMA, "rx dma write paddr=%#x len=%d\n",
|
|
rxDmaAddr, rxDmaLen);
|
|
DDUMP(EthernetData, rxDmaData, rxDmaLen);
|
|
}
|
|
|
|
void
|
|
Device::rxDmaDone()
|
|
{
|
|
rxDmaCopy();
|
|
|
|
// If the transmit state machine has a pending DMA, let it go first
|
|
if (txState == txBeginCopy)
|
|
txKick();
|
|
|
|
rxKick();
|
|
}
|
|
|
|
void
|
|
Device::rxKick()
|
|
{
|
|
VirtualReg *vnic;
|
|
|
|
DPRINTF(EthernetSM, "receive kick rxState=%s (rxFifo.size=%d)\n",
|
|
RxStateStrings[rxState], rxFifo.size());
|
|
|
|
if (rxKickTick > curTick) {
|
|
DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
|
|
rxKickTick);
|
|
return;
|
|
}
|
|
|
|
next:
|
|
if (rxState == rxIdle)
|
|
goto exit;
|
|
|
|
assert(!rxList.empty());
|
|
vnic = &virtualRegs[rxList.front()];
|
|
|
|
DPRINTF(EthernetSM, "processing rxState=%s for virtual nic %d\n",
|
|
RxStateStrings[rxState], rxList.front());
|
|
|
|
switch (rxState) {
|
|
case rxFifoBlock:
|
|
if (vnic->rxPacket != rxFifo.end()) {
|
|
rxState = rxBeginCopy;
|
|
break;
|
|
}
|
|
|
|
if (rxFifoPtr == rxFifo.end()) {
|
|
DPRINTF(EthernetSM, "receive waiting for data. Nothing to do.\n");
|
|
goto exit;
|
|
}
|
|
|
|
assert(!rxFifo.empty());
|
|
|
|
// Grab a new packet from the fifo.
|
|
vnic->rxPacket = rxFifoPtr++;
|
|
vnic->rxPacketOffset = 0;
|
|
vnic->rxPacketBytes = (*vnic->rxPacket)->length;
|
|
assert(vnic->rxPacketBytes);
|
|
|
|
vnic->rxDoneData = 0;
|
|
/* scope for variables */ {
|
|
IpPtr ip(*vnic->rxPacket);
|
|
if (ip) {
|
|
vnic->rxDoneData |= Regs::RxDone_IpPacket;
|
|
rxIpChecksums++;
|
|
if (cksum(ip) != 0) {
|
|
DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
|
|
vnic->rxDoneData |= Regs::RxDone_IpError;
|
|
}
|
|
TcpPtr tcp(ip);
|
|
UdpPtr udp(ip);
|
|
if (tcp) {
|
|
vnic->rxDoneData |= Regs::RxDone_TcpPacket;
|
|
rxTcpChecksums++;
|
|
if (cksum(tcp) != 0) {
|
|
DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
|
|
vnic->rxDoneData |= Regs::RxDone_TcpError;
|
|
}
|
|
} else if (udp) {
|
|
vnic->rxDoneData |= Regs::RxDone_UdpPacket;
|
|
rxUdpChecksums++;
|
|
if (cksum(udp) != 0) {
|
|
DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
|
|
vnic->rxDoneData |= Regs::RxDone_UdpError;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
rxState = rxBeginCopy;
|
|
break;
|
|
|
|
case rxBeginCopy:
|
|
if (dmaInterface && dmaInterface->busy())
|
|
goto exit;
|
|
|
|
rxDmaAddr = plat->pciToDma(Regs::get_RxData_Addr(vnic->RxData));
|
|
rxDmaLen = min<int>(Regs::get_RxData_Len(vnic->RxData),
|
|
vnic->rxPacketBytes);
|
|
rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
|
|
rxState = rxCopy;
|
|
|
|
if (dmaInterface) {
|
|
dmaInterface->doDMA(WriteInvalidate, rxDmaAddr, rxDmaLen,
|
|
curTick, &rxDmaEvent, true);
|
|
goto exit;
|
|
}
|
|
|
|
if (dmaWriteDelay != 0 || dmaWriteFactor != 0) {
|
|
Tick factor = ((rxDmaLen + ULL(63)) >> ULL(6)) * dmaWriteFactor;
|
|
Tick start = curTick + dmaWriteDelay + factor;
|
|
rxDmaEvent.schedule(start);
|
|
goto exit;
|
|
}
|
|
|
|
rxDmaCopy();
|
|
break;
|
|
|
|
case rxCopy:
|
|
DPRINTF(EthernetSM, "receive machine still copying\n");
|
|
goto exit;
|
|
|
|
case rxCopyDone:
|
|
vnic->RxDone = vnic->rxDoneData | rxDmaLen;
|
|
vnic->RxDone |= Regs::RxDone_Complete;
|
|
|
|
if (vnic->rxPacketBytes == rxDmaLen) {
|
|
DPRINTF(EthernetSM, "rxKick: packet complete on vnic %d\n",
|
|
rxList.front());
|
|
rxFifo.remove(vnic->rxPacket);
|
|
vnic->rxPacket = rxFifo.end();
|
|
} else {
|
|
vnic->RxDone |= Regs::RxDone_More;
|
|
vnic->rxPacketBytes -= rxDmaLen;
|
|
vnic->rxPacketOffset += rxDmaLen;
|
|
DPRINTF(EthernetSM,
|
|
"rxKick: packet not complete on vnic %d: %d bytes left\n",
|
|
rxList.front(), vnic->rxPacketBytes);
|
|
}
|
|
|
|
rxList.pop_front();
|
|
rxState = rxList.empty() ? rxIdle : rxFifoBlock;
|
|
|
|
if (rxFifo.empty()) {
|
|
devIntrPost(Regs::Intr_RxEmpty);
|
|
rxEmpty = true;
|
|
}
|
|
|
|
devIntrPost(Regs::Intr_RxDMA);
|
|
break;
|
|
|
|
default:
|
|
panic("Invalid rxState!");
|
|
}
|
|
|
|
DPRINTF(EthernetSM, "entering next rxState=%s\n",
|
|
RxStateStrings[rxState]);
|
|
|
|
goto next;
|
|
|
|
exit:
|
|
/**
|
|
* @todo do we want to schedule a future kick?
|
|
*/
|
|
DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n",
|
|
RxStateStrings[rxState]);
|
|
}
|
|
|
|
void
|
|
Device::txDmaCopy()
|
|
{
|
|
assert(txState == txCopy);
|
|
txState = txCopyDone;
|
|
physmem->dma_read((uint8_t *)txDmaData, txDmaAddr, txDmaLen);
|
|
DPRINTF(EthernetDMA, "tx dma read paddr=%#x len=%d\n",
|
|
txDmaAddr, txDmaLen);
|
|
DDUMP(EthernetData, txDmaData, txDmaLen);
|
|
}
|
|
|
|
void
|
|
Device::txDmaDone()
|
|
{
|
|
txDmaCopy();
|
|
|
|
// If the receive state machine has a pending DMA, let it go first
|
|
if (rxState == rxBeginCopy)
|
|
rxKick();
|
|
|
|
txKick();
|
|
}
|
|
|
|
void
|
|
Device::transmit()
|
|
{
|
|
if (txFifo.empty()) {
|
|
DPRINTF(Ethernet, "nothing to transmit\n");
|
|
return;
|
|
}
|
|
|
|
uint32_t interrupts;
|
|
PacketPtr packet = txFifo.front();
|
|
if (!interface->sendPacket(packet)) {
|
|
DPRINTF(Ethernet, "Packet Transmit: failed txFifo available %d\n",
|
|
txFifo.avail());
|
|
goto reschedule;
|
|
}
|
|
|
|
txFifo.pop();
|
|
#if TRACING_ON
|
|
if (DTRACE(Ethernet)) {
|
|
IpPtr ip(packet);
|
|
if (ip) {
|
|
DPRINTF(Ethernet, "ID is %d\n", ip->id());
|
|
TcpPtr tcp(ip);
|
|
if (tcp) {
|
|
DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
|
|
tcp->sport(), tcp->dport());
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
DDUMP(EthernetData, packet->data, packet->length);
|
|
txBytes += packet->length;
|
|
txPackets++;
|
|
|
|
DPRINTF(Ethernet, "Packet Transmit: successful txFifo Available %d\n",
|
|
txFifo.avail());
|
|
|
|
interrupts = Regs::Intr_TxPacket;
|
|
if (txFifo.size() < regs.TxFifoMark)
|
|
interrupts |= Regs::Intr_TxLow;
|
|
devIntrPost(interrupts);
|
|
|
|
reschedule:
|
|
if (!txFifo.empty() && !txEvent.scheduled()) {
|
|
DPRINTF(Ethernet, "reschedule transmit\n");
|
|
txEvent.schedule(curTick + retryTime);
|
|
}
|
|
}
|
|
|
|
void
|
|
Device::txKick()
|
|
{
|
|
VirtualReg *vnic;
|
|
DPRINTF(EthernetSM, "transmit kick txState=%s (txFifo.size=%d)\n",
|
|
TxStateStrings[txState], txFifo.size());
|
|
|
|
if (txKickTick > curTick) {
|
|
DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
|
|
txKickTick);
|
|
return;
|
|
}
|
|
|
|
next:
|
|
if (txState == txIdle)
|
|
goto exit;
|
|
|
|
assert(!txList.empty());
|
|
vnic = &virtualRegs[txList.front()];
|
|
|
|
switch (txState) {
|
|
case txFifoBlock:
|
|
assert(Regs::get_TxDone_Busy(vnic->TxData));
|
|
if (!txPacket) {
|
|
// Grab a new packet from the fifo.
|
|
txPacket = new PacketData(16384);
|
|
txPacketOffset = 0;
|
|
}
|
|
|
|
if (txFifo.avail() - txPacket->length <
|
|
Regs::get_TxData_Len(vnic->TxData)) {
|
|
DPRINTF(EthernetSM, "transmit fifo full. Nothing to do.\n");
|
|
goto exit;
|
|
}
|
|
|
|
txState = txBeginCopy;
|
|
break;
|
|
|
|
case txBeginCopy:
|
|
if (dmaInterface && dmaInterface->busy())
|
|
goto exit;
|
|
|
|
txDmaAddr = plat->pciToDma(Regs::get_TxData_Addr(vnic->TxData));
|
|
txDmaLen = Regs::get_TxData_Len(vnic->TxData);
|
|
txDmaData = txPacket->data + txPacketOffset;
|
|
txState = txCopy;
|
|
|
|
if (dmaInterface) {
|
|
dmaInterface->doDMA(Read, txDmaAddr, txDmaLen,
|
|
curTick, &txDmaEvent, true);
|
|
goto exit;
|
|
}
|
|
|
|
if (dmaReadDelay != 0 || dmaReadFactor != 0) {
|
|
Tick factor = ((txDmaLen + ULL(63)) >> ULL(6)) * dmaReadFactor;
|
|
Tick start = curTick + dmaReadDelay + factor;
|
|
txDmaEvent.schedule(start);
|
|
goto exit;
|
|
}
|
|
|
|
txDmaCopy();
|
|
break;
|
|
|
|
case txCopy:
|
|
DPRINTF(EthernetSM, "transmit machine still copying\n");
|
|
goto exit;
|
|
|
|
case txCopyDone:
|
|
vnic->TxDone = txDmaLen | Regs::TxDone_Complete;
|
|
txPacket->length += txDmaLen;
|
|
if ((vnic->TxData & Regs::TxData_More)) {
|
|
txPacketOffset += txDmaLen;
|
|
txState = txIdle;
|
|
devIntrPost(Regs::Intr_TxDMA);
|
|
break;
|
|
}
|
|
|
|
assert(txPacket->length <= txFifo.avail());
|
|
if ((vnic->TxData & Regs::TxData_Checksum)) {
|
|
IpPtr ip(txPacket);
|
|
if (ip) {
|
|
TcpPtr tcp(ip);
|
|
if (tcp) {
|
|
tcp->sum(0);
|
|
tcp->sum(cksum(tcp));
|
|
txTcpChecksums++;
|
|
}
|
|
|
|
UdpPtr udp(ip);
|
|
if (udp) {
|
|
udp->sum(0);
|
|
udp->sum(cksum(udp));
|
|
txUdpChecksums++;
|
|
}
|
|
|
|
ip->sum(0);
|
|
ip->sum(cksum(ip));
|
|
txIpChecksums++;
|
|
}
|
|
}
|
|
|
|
txFifo.push(txPacket);
|
|
if (txFifo.avail() < regs.TxMaxCopy) {
|
|
devIntrPost(Regs::Intr_TxFull);
|
|
txFull = true;
|
|
}
|
|
txPacket = 0;
|
|
transmit();
|
|
txList.pop_front();
|
|
txState = txList.empty() ? txIdle : txFifoBlock;
|
|
devIntrPost(Regs::Intr_TxDMA);
|
|
break;
|
|
|
|
default:
|
|
panic("Invalid txState!");
|
|
}
|
|
|
|
DPRINTF(EthernetSM, "entering next txState=%s\n",
|
|
TxStateStrings[txState]);
|
|
|
|
goto next;
|
|
|
|
exit:
|
|
/**
|
|
* @todo do we want to schedule a future kick?
|
|
*/
|
|
DPRINTF(EthernetSM, "tx state machine exited txState=%s\n",
|
|
TxStateStrings[txState]);
|
|
}
|
|
|
|
void
|
|
Device::transferDone()
|
|
{
|
|
if (txFifo.empty()) {
|
|
DPRINTF(Ethernet, "transfer complete: txFifo empty...nothing to do\n");
|
|
return;
|
|
}
|
|
|
|
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
|
|
|
if (txEvent.scheduled())
|
|
txEvent.reschedule(curTick + cycles(1));
|
|
else
|
|
txEvent.schedule(curTick + cycles(1));
|
|
}
|
|
|
|
bool
|
|
Device::rxFilter(const PacketPtr &packet)
|
|
{
|
|
if (!Regs::get_Config_Filter(regs.Config))
|
|
return false;
|
|
|
|
panic("receive filter not implemented\n");
|
|
bool drop = true;
|
|
|
|
#if 0
|
|
string type;
|
|
|
|
EthHdr *eth = packet->eth();
|
|
if (eth->unicast()) {
|
|
// If we're accepting all unicast addresses
|
|
if (acceptUnicast)
|
|
drop = false;
|
|
|
|
// If we make a perfect match
|
|
if (acceptPerfect && params->eaddr == eth.dst())
|
|
drop = false;
|
|
|
|
if (acceptArp && eth->type() == ETH_TYPE_ARP)
|
|
drop = false;
|
|
|
|
} else if (eth->broadcast()) {
|
|
// if we're accepting broadcasts
|
|
if (acceptBroadcast)
|
|
drop = false;
|
|
|
|
} else if (eth->multicast()) {
|
|
// if we're accepting all multicasts
|
|
if (acceptMulticast)
|
|
drop = false;
|
|
|
|
}
|
|
|
|
if (drop) {
|
|
DPRINTF(Ethernet, "rxFilter drop\n");
|
|
DDUMP(EthernetData, packet->data, packet->length);
|
|
}
|
|
#endif
|
|
return drop;
|
|
}
|
|
|
|
bool
|
|
Device::recvPacket(PacketPtr packet)
|
|
{
|
|
rxBytes += packet->length;
|
|
rxPackets++;
|
|
|
|
DPRINTF(Ethernet, "Receiving packet from wire, rxFifo Available is %d\n",
|
|
rxFifo.avail());
|
|
|
|
if (!rxEnable) {
|
|
DPRINTF(Ethernet, "receive disabled...packet dropped\n");
|
|
return true;
|
|
}
|
|
|
|
if (rxFilter(packet)) {
|
|
DPRINTF(Ethernet, "packet filtered...dropped\n");
|
|
return true;
|
|
}
|
|
|
|
if (rxFifo.size() >= regs.RxFifoMark)
|
|
devIntrPost(Regs::Intr_RxHigh);
|
|
|
|
if (!rxFifo.push(packet)) {
|
|
DPRINTF(Ethernet,
|
|
"packet will not fit in receive buffer...packet dropped\n");
|
|
return false;
|
|
}
|
|
|
|
// If we were at the last element, back up one ot go to the new
|
|
// last element of the list.
|
|
if (rxFifoPtr == rxFifo.end())
|
|
--rxFifoPtr;
|
|
|
|
devIntrPost(Regs::Intr_RxPacket);
|
|
rxKick();
|
|
return true;
|
|
}
|
|
|
|
//=====================================================================
|
|
//
|
|
//
|
|
void
|
|
Base::serialize(ostream &os)
|
|
{
|
|
// Serialize the PciDev base class
|
|
PciDev::serialize(os);
|
|
|
|
SERIALIZE_SCALAR(rxEnable);
|
|
SERIALIZE_SCALAR(txEnable);
|
|
SERIALIZE_SCALAR(cpuIntrEnable);
|
|
|
|
/*
|
|
* Keep track of pending interrupt status.
|
|
*/
|
|
SERIALIZE_SCALAR(intrTick);
|
|
SERIALIZE_SCALAR(cpuPendingIntr);
|
|
Tick intrEventTick = 0;
|
|
if (intrEvent)
|
|
intrEventTick = intrEvent->when();
|
|
SERIALIZE_SCALAR(intrEventTick);
|
|
}
|
|
|
|
void
|
|
Base::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
// Unserialize the PciDev base class
|
|
PciDev::unserialize(cp, section);
|
|
|
|
UNSERIALIZE_SCALAR(rxEnable);
|
|
UNSERIALIZE_SCALAR(txEnable);
|
|
UNSERIALIZE_SCALAR(cpuIntrEnable);
|
|
|
|
/*
|
|
* Keep track of pending interrupt status.
|
|
*/
|
|
UNSERIALIZE_SCALAR(intrTick);
|
|
UNSERIALIZE_SCALAR(cpuPendingIntr);
|
|
Tick intrEventTick;
|
|
UNSERIALIZE_SCALAR(intrEventTick);
|
|
if (intrEventTick) {
|
|
intrEvent = new IntrEvent(this, true);
|
|
intrEvent->schedule(intrEventTick);
|
|
}
|
|
}
|
|
|
|
void
|
|
Device::serialize(ostream &os)
|
|
{
|
|
// Serialize the PciDev base class
|
|
Base::serialize(os);
|
|
|
|
if (rxState == rxCopy)
|
|
panic("can't serialize with an in flight dma request rxState=%s",
|
|
RxStateStrings[rxState]);
|
|
|
|
if (txState == txCopy)
|
|
panic("can't serialize with an in flight dma request txState=%s",
|
|
TxStateStrings[txState]);
|
|
|
|
/*
|
|
* Serialize the device registers
|
|
*/
|
|
SERIALIZE_SCALAR(regs.Config);
|
|
SERIALIZE_SCALAR(regs.IntrStatus);
|
|
SERIALIZE_SCALAR(regs.IntrMask);
|
|
SERIALIZE_SCALAR(regs.RxMaxCopy);
|
|
SERIALIZE_SCALAR(regs.TxMaxCopy);
|
|
SERIALIZE_SCALAR(regs.RxMaxIntr);
|
|
SERIALIZE_SCALAR(regs.RxData);
|
|
SERIALIZE_SCALAR(regs.RxDone);
|
|
SERIALIZE_SCALAR(regs.TxData);
|
|
SERIALIZE_SCALAR(regs.TxDone);
|
|
|
|
/*
|
|
* Serialize the virtual nic state
|
|
*/
|
|
int virtualRegsSize = virtualRegs.size();
|
|
SERIALIZE_SCALAR(virtualRegsSize);
|
|
for (int i = 0; i < virtualRegsSize; ++i) {
|
|
VirtualReg *vnic = &virtualRegs[i];
|
|
|
|
string reg = csprintf("vnic%d", i);
|
|
paramOut(os, reg + ".RxData", vnic->RxData);
|
|
paramOut(os, reg + ".RxDone", vnic->RxDone);
|
|
paramOut(os, reg + ".TxData", vnic->TxData);
|
|
paramOut(os, reg + ".TxDone", vnic->TxDone);
|
|
|
|
PacketFifo::iterator rxFifoPtr;
|
|
|
|
bool rxPacketExists = vnic->rxPacket != rxFifo.end();
|
|
paramOut(os, reg + ".rxPacketExists", rxPacketExists);
|
|
if (rxPacketExists) {
|
|
int rxPacket = 0;
|
|
PacketFifo::iterator i = rxFifo.begin();
|
|
while (i != vnic->rxPacket) {
|
|
assert(i != rxFifo.end());
|
|
++i;
|
|
++rxPacket;
|
|
}
|
|
|
|
paramOut(os, reg + ".rxPacket", rxPacket);
|
|
paramOut(os, reg + ".rxPacketOffset", vnic->rxPacketOffset);
|
|
paramOut(os, reg + ".rxPacketBytes", vnic->rxPacketBytes);
|
|
}
|
|
paramOut(os, reg + ".rxDoneData", vnic->rxDoneData);
|
|
}
|
|
|
|
VirtualList::iterator i, end;
|
|
int count;
|
|
|
|
int rxListSize = rxList.size();
|
|
SERIALIZE_SCALAR(rxListSize);
|
|
for (count = 0, i = rxList.begin(), end = rxList.end(); i != end; ++i)
|
|
paramOut(os, csprintf("rxList%d", count++), *i);
|
|
|
|
int txListSize = txList.size();
|
|
SERIALIZE_SCALAR(txListSize);
|
|
for (count = 0, i = txList.begin(), end = txList.end(); i != end; ++i)
|
|
paramOut(os, csprintf("txList%d", count++), *i);
|
|
|
|
/*
|
|
* Serialize rx state machine
|
|
*/
|
|
int rxState = this->rxState;
|
|
SERIALIZE_SCALAR(rxState);
|
|
SERIALIZE_SCALAR(rxEmpty);
|
|
rxFifo.serialize("rxFifo", os);
|
|
|
|
/*
|
|
* Serialize tx state machine
|
|
*/
|
|
int txState = this->txState;
|
|
SERIALIZE_SCALAR(txState);
|
|
SERIALIZE_SCALAR(txFull);
|
|
txFifo.serialize("txFifo", os);
|
|
bool txPacketExists = txPacket;
|
|
SERIALIZE_SCALAR(txPacketExists);
|
|
if (txPacketExists) {
|
|
txPacket->serialize("txPacket", os);
|
|
SERIALIZE_SCALAR(txPacketOffset);
|
|
SERIALIZE_SCALAR(txPacketBytes);
|
|
}
|
|
|
|
/*
|
|
* If there's a pending transmit, store the time so we can
|
|
* reschedule it later
|
|
*/
|
|
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
|
|
SERIALIZE_SCALAR(transmitTick);
|
|
}
|
|
|
|
void
|
|
Device::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
// Unserialize the PciDev base class
|
|
Base::unserialize(cp, section);
|
|
|
|
/*
|
|
* Unserialize the device registers
|
|
*/
|
|
UNSERIALIZE_SCALAR(regs.Config);
|
|
UNSERIALIZE_SCALAR(regs.IntrStatus);
|
|
UNSERIALIZE_SCALAR(regs.IntrMask);
|
|
UNSERIALIZE_SCALAR(regs.RxMaxCopy);
|
|
UNSERIALIZE_SCALAR(regs.TxMaxCopy);
|
|
UNSERIALIZE_SCALAR(regs.RxMaxIntr);
|
|
UNSERIALIZE_SCALAR(regs.RxData);
|
|
UNSERIALIZE_SCALAR(regs.RxDone);
|
|
UNSERIALIZE_SCALAR(regs.TxData);
|
|
UNSERIALIZE_SCALAR(regs.TxDone);
|
|
|
|
int rxListSize;
|
|
UNSERIALIZE_SCALAR(rxListSize);
|
|
rxList.clear();
|
|
for (int i = 0; i < rxListSize; ++i) {
|
|
int value;
|
|
paramIn(cp, section, csprintf("rxList%d", i), value);
|
|
rxList.push_back(value);
|
|
}
|
|
|
|
int txListSize;
|
|
UNSERIALIZE_SCALAR(txListSize);
|
|
txList.clear();
|
|
for (int i = 0; i < txListSize; ++i) {
|
|
int value;
|
|
paramIn(cp, section, csprintf("txList%d", i), value);
|
|
txList.push_back(value);
|
|
}
|
|
|
|
/*
|
|
* Unserialize rx state machine
|
|
*/
|
|
int rxState;
|
|
UNSERIALIZE_SCALAR(rxState);
|
|
UNSERIALIZE_SCALAR(rxEmpty);
|
|
this->rxState = (RxState) rxState;
|
|
rxFifo.unserialize("rxFifo", cp, section);
|
|
|
|
/*
|
|
* Unserialize tx state machine
|
|
*/
|
|
int txState;
|
|
UNSERIALIZE_SCALAR(txState);
|
|
UNSERIALIZE_SCALAR(txFull);
|
|
this->txState = (TxState) txState;
|
|
txFifo.unserialize("txFifo", cp, section);
|
|
bool txPacketExists;
|
|
UNSERIALIZE_SCALAR(txPacketExists);
|
|
txPacket = 0;
|
|
if (txPacketExists) {
|
|
txPacket = new PacketData(16384);
|
|
txPacket->unserialize("txPacket", cp, section);
|
|
UNSERIALIZE_SCALAR(txPacketOffset);
|
|
UNSERIALIZE_SCALAR(txPacketBytes);
|
|
}
|
|
|
|
/*
|
|
* unserialize the virtual nic registers/state
|
|
*
|
|
* this must be done after the unserialization of the rxFifo
|
|
* because the packet iterators depend on the fifo being populated
|
|
*/
|
|
int virtualRegsSize;
|
|
UNSERIALIZE_SCALAR(virtualRegsSize);
|
|
virtualRegs.clear();
|
|
virtualRegs.resize(virtualRegsSize);
|
|
for (int i = 0; i < virtualRegsSize; ++i) {
|
|
VirtualReg *vnic = &virtualRegs[i];
|
|
string reg = csprintf("vnic%d", i);
|
|
|
|
paramIn(cp, section, reg + ".RxData", vnic->RxData);
|
|
paramIn(cp, section, reg + ".RxDone", vnic->RxDone);
|
|
paramIn(cp, section, reg + ".TxData", vnic->TxData);
|
|
paramIn(cp, section, reg + ".TxDone", vnic->TxDone);
|
|
|
|
bool rxPacketExists;
|
|
paramIn(cp, section, reg + ".rxPacketExists", rxPacketExists);
|
|
if (rxPacketExists) {
|
|
int rxPacket;
|
|
paramIn(cp, section, reg + ".rxPacket", rxPacket);
|
|
vnic->rxPacket = rxFifo.begin();
|
|
while (rxPacket--)
|
|
++vnic->rxPacket;
|
|
|
|
paramIn(cp, section, reg + ".rxPacketOffset",
|
|
vnic->rxPacketOffset);
|
|
paramIn(cp, section, reg + ".rxPacketBytes", vnic->rxPacketBytes);
|
|
} else {
|
|
vnic->rxPacket = rxFifo.end();
|
|
}
|
|
paramIn(cp, section, reg + ".rxDoneData", vnic->rxDoneData);
|
|
}
|
|
|
|
/*
|
|
* If there's a pending transmit, reschedule it now
|
|
*/
|
|
Tick transmitTick;
|
|
UNSERIALIZE_SCALAR(transmitTick);
|
|
if (transmitTick)
|
|
txEvent.schedule(curTick + transmitTick);
|
|
|
|
/*
|
|
* re-add addrRanges to bus bridges
|
|
*/
|
|
if (pioInterface) {
|
|
pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
|
|
pioInterface->addAddrRange(RangeSize(BARAddrs[1], BARSize[1]));
|
|
}
|
|
}
|
|
|
|
Tick
|
|
Device::cacheAccess(MemReqPtr &req)
|
|
{
|
|
Addr daddr;
|
|
int bar;
|
|
if (!getBAR(req->paddr, daddr, bar))
|
|
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
|
|
req->paddr, req->vaddr, req->size);
|
|
|
|
DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n",
|
|
req->cmd.toString(), req->paddr, bar, daddr);
|
|
|
|
return curTick + pioLatency;
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Interface)
|
|
|
|
SimObjectParam<EtherInt *> peer;
|
|
SimObjectParam<Device *> device;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(Interface)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(Interface)
|
|
|
|
INIT_PARAM_DFLT(peer, "peer interface", NULL),
|
|
INIT_PARAM(device, "Ethernet device of this interface")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(Interface)
|
|
|
|
CREATE_SIM_OBJECT(Interface)
|
|
{
|
|
Interface *dev_int = new Interface(getInstanceName(), device);
|
|
|
|
EtherInt *p = (EtherInt *)peer;
|
|
if (p) {
|
|
dev_int->setPeer(p);
|
|
p->setPeer(dev_int);
|
|
}
|
|
|
|
return dev_int;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SinicInt", Interface)
|
|
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
|
|
|
|
Param<Tick> clock;
|
|
|
|
Param<Addr> addr;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
SimObjectParam<PhysicalMemory *> physmem;
|
|
SimObjectParam<PciConfigAll *> configspace;
|
|
SimObjectParam<PciConfigData *> configdata;
|
|
SimObjectParam<Platform *> platform;
|
|
Param<uint32_t> pci_bus;
|
|
Param<uint32_t> pci_dev;
|
|
Param<uint32_t> pci_func;
|
|
|
|
SimObjectParam<HierParams *> hier;
|
|
SimObjectParam<Bus*> pio_bus;
|
|
SimObjectParam<Bus*> dma_bus;
|
|
SimObjectParam<Bus*> payload_bus;
|
|
Param<Tick> dma_read_delay;
|
|
Param<Tick> dma_read_factor;
|
|
Param<Tick> dma_write_delay;
|
|
Param<Tick> dma_write_factor;
|
|
Param<bool> dma_no_allocate;
|
|
Param<Tick> pio_latency;
|
|
Param<Tick> intr_delay;
|
|
|
|
Param<Tick> rx_delay;
|
|
Param<Tick> tx_delay;
|
|
Param<uint32_t> rx_max_copy;
|
|
Param<uint32_t> tx_max_copy;
|
|
Param<uint32_t> rx_max_intr;
|
|
Param<uint32_t> rx_fifo_size;
|
|
Param<uint32_t> tx_fifo_size;
|
|
Param<uint32_t> rx_fifo_threshold;
|
|
Param<uint32_t> tx_fifo_threshold;
|
|
|
|
Param<bool> rx_filter;
|
|
Param<string> hardware_address;
|
|
Param<bool> rx_thread;
|
|
Param<bool> tx_thread;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(Device)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
|
|
|
|
INIT_PARAM(clock, "State machine cycle time"),
|
|
|
|
INIT_PARAM(addr, "Device Address"),
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
|
INIT_PARAM(physmem, "Physical Memory"),
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|
INIT_PARAM(configspace, "PCI Configspace"),
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|
INIT_PARAM(configdata, "PCI Config data"),
|
|
INIT_PARAM(platform, "Platform"),
|
|
INIT_PARAM(pci_bus, "PCI bus"),
|
|
INIT_PARAM(pci_dev, "PCI device number"),
|
|
INIT_PARAM(pci_func, "PCI function code"),
|
|
|
|
INIT_PARAM(hier, "Hierarchy global variables"),
|
|
INIT_PARAM(pio_bus, ""),
|
|
INIT_PARAM(dma_bus, ""),
|
|
INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
|
|
INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
|
|
INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
|
|
INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
|
|
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
|
|
INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
|
|
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
|
|
INIT_PARAM(intr_delay, "Interrupt Delay"),
|
|
|
|
INIT_PARAM(rx_delay, "Receive Delay"),
|
|
INIT_PARAM(tx_delay, "Transmit Delay"),
|
|
INIT_PARAM(rx_max_copy, "rx max copy"),
|
|
INIT_PARAM(tx_max_copy, "rx max copy"),
|
|
INIT_PARAM(rx_max_intr, "rx max intr"),
|
|
INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
|
|
INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
|
|
INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
|
|
INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
|
|
|
|
INIT_PARAM(rx_filter, "Enable Receive Filter"),
|
|
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
|
|
INIT_PARAM(rx_thread, ""),
|
|
INIT_PARAM(tx_thread, "")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(Device)
|
|
|
|
|
|
CREATE_SIM_OBJECT(Device)
|
|
{
|
|
Device::Params *params = new Device::Params;
|
|
|
|
params->name = getInstanceName();
|
|
|
|
params->clock = clock;
|
|
|
|
params->mmu = mmu;
|
|
params->physmem = physmem;
|
|
params->configSpace = configspace;
|
|
params->configData = configdata;
|
|
params->plat = platform;
|
|
params->busNum = pci_bus;
|
|
params->deviceNum = pci_dev;
|
|
params->functionNum = pci_func;
|
|
|
|
params->hier = hier;
|
|
params->pio_bus = pio_bus;
|
|
params->header_bus = dma_bus;
|
|
params->payload_bus = payload_bus;
|
|
params->dma_read_delay = dma_read_delay;
|
|
params->dma_read_factor = dma_read_factor;
|
|
params->dma_write_delay = dma_write_delay;
|
|
params->dma_write_factor = dma_write_factor;
|
|
params->dma_no_allocate = dma_no_allocate;
|
|
params->pio_latency = pio_latency;
|
|
params->intr_delay = intr_delay;
|
|
|
|
params->tx_delay = tx_delay;
|
|
params->rx_delay = rx_delay;
|
|
params->rx_max_copy = rx_max_copy;
|
|
params->tx_max_copy = tx_max_copy;
|
|
params->rx_max_intr = rx_max_intr;
|
|
params->rx_fifo_size = rx_fifo_size;
|
|
params->tx_fifo_size = tx_fifo_size;
|
|
params->rx_fifo_threshold = rx_fifo_threshold;
|
|
params->tx_fifo_threshold = tx_fifo_threshold;
|
|
|
|
params->rx_filter = rx_filter;
|
|
params->eaddr = hardware_address;
|
|
params->rx_thread = rx_thread;
|
|
params->tx_thread = tx_thread;
|
|
|
|
return new Device(params);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("Sinic", Device)
|
|
|
|
/* namespace Sinic */ }
|