gem5/dev/simconsole.cc
Steve Reinhardt ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00

415 lines
9.1 KiB
C++

/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* Implements the user interface to a serial console
*/
#include <sys/ioctl.h>
#include <sys/termios.h>
#include <sys/types.h>
#include <errno.h>
#include <poll.h>
#include <unistd.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include "base/misc.hh"
#include "base/output.hh"
#include "base/socket.hh"
#include "base/trace.hh"
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
////////////////////////////////////////////////////////////////////////
//
//
SimConsole::Event::Event(SimConsole *c, int fd, int e)
: PollEvent(fd, e), cons(c)
{
}
void
SimConsole::Event::process(int revent)
{
if (revent & POLLIN)
cons->data();
else if (revent & POLLNVAL)
cons->detach();
}
SimConsole::SimConsole(const string &name, ostream *os, int num)
: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
listener(NULL), txbuf(16384), rxbuf(16384), outfile(os)
#if TRACING_ON == 1
, linebuf(16384)
#endif
{
if (outfile)
outfile->setf(ios::unitbuf);
}
SimConsole::~SimConsole()
{
close();
}
void
SimConsole::close()
{
if (in_fd != -1)
::close(in_fd);
if (out_fd != in_fd && out_fd != -1)
::close(out_fd);
}
void
SimConsole::attach(int in, int out, ConsoleListener *l)
{
in_fd = in;
out_fd = out;
listener = l;
event = new Event(this, in, POLLIN);
pollQueue.schedule(event);
stringstream stream;
ccprintf(stream, "==== m5 slave console: Console %d ====", number);
// we need an actual carriage return followed by a newline for the
// terminal
stream << "\r\n";
write((const uint8_t *)stream.str().c_str(), stream.str().size());
DPRINTFN("attach console %d\n", number);
txbuf.readall(out);
}
void
SimConsole::detach()
{
close();
in_fd = -1;
out_fd = -1;
pollQueue.remove(event);
if (listener) {
listener->add(this);
listener = NULL;
}
DPRINTFN("detach console %d\n", number);
}
void
SimConsole::data()
{
uint8_t buf[1024];
int len;
len = read(buf, sizeof(buf));
if (len) {
rxbuf.write((char *)buf, len);
// Inform the UART there is data available
uart->dataAvailable();
}
}
size_t
SimConsole::read(uint8_t *buf, size_t len)
{
if (in_fd < 0)
panic("Console not properly attached.\n");
size_t ret;
do {
ret = ::read(in_fd, buf, len);
} while (ret == -1 && errno == EINTR);
if (ret < 0)
DPRINTFN("Read failed.\n");
if (ret <= 0) {
detach();
return 0;
}
return ret;
}
// Console output.
size_t
SimConsole::write(const uint8_t *buf, size_t len)
{
if (out_fd < 0)
panic("Console not properly attached.\n");
size_t ret;
for (;;) {
ret = ::write(out_fd, buf, len);
if (ret >= 0)
break;
if (errno != EINTR)
detach();
}
return ret;
}
#define MORE_PENDING (ULL(1) << 61)
#define RECEIVE_SUCCESS (ULL(0) << 62)
#define RECEIVE_NONE (ULL(2) << 62)
#define RECEIVE_ERROR (ULL(3) << 62)
bool
SimConsole::in(uint8_t &c)
{
bool empty, ret;
empty = rxbuf.empty();
ret = !empty;
if (!empty) {
rxbuf.read((char *)&c, 1);
empty = rxbuf.empty();
}
DPRINTF(ConsoleVerbose, "in: \'%c\' %#02x more: %d, return: %d\n",
isprint(c) ? c : ' ', c, !empty, ret);
return ret;
}
uint64_t
SimConsole::console_in()
{
uint8_t c;
uint64_t value;
if (in(c)) {
value = RECEIVE_SUCCESS | c;
if (!rxbuf.empty())
value |= MORE_PENDING;
} else {
value = RECEIVE_NONE;
}
DPRINTF(ConsoleVerbose, "console_in: return: %#x\n", value);
return value;
}
void
SimConsole::out(char c)
{
#if TRACING_ON == 1
if (DTRACE(Console)) {
static char last = '\0';
if (c != '\n' && c != '\r' ||
last != '\n' && last != '\r') {
if (c == '\n' || c == '\r') {
int size = linebuf.size();
char *buffer = new char[size + 1];
linebuf.read(buffer, size);
buffer[size] = '\0';
DPRINTF(Console, "%s\n", buffer);
delete [] buffer;
} else {
linebuf.write(c);
}
}
last = c;
}
#endif
txbuf.write(c);
if (out_fd >= 0)
write(c);
if (outfile)
outfile->write(&c, 1);
DPRINTF(ConsoleVerbose, "out: \'%c\' %#02x\n",
isprint(c) ? c : ' ', (int)c);
}
void
SimConsole::serialize(ostream &os)
{
}
void
SimConsole::unserialize(Checkpoint *cp, const std::string &section)
{
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
SimObjectParam<ConsoleListener *> listener;
SimObjectParam<IntrControl *> intr_control;
Param<string> output;
Param<bool> append_name;
Param<int> number;
END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
INIT_PARAM(listener, "console listener"),
INIT_PARAM(intr_control, "interrupt controller"),
INIT_PARAM(output, "file to dump output to"),
INIT_PARAM_DFLT(append_name, "append name() to filename", true),
INIT_PARAM_DFLT(number, "console number", 0)
END_INIT_SIM_OBJECT_PARAMS(SimConsole)
CREATE_SIM_OBJECT(SimConsole)
{
string filename = output;
ostream *stream = NULL;
if (!filename.empty()) {
if (append_name)
filename += "." + getInstanceName();
stream = simout.find(filename);
}
SimConsole *console = new SimConsole(getInstanceName(), stream, number);
((ConsoleListener *)listener)->add(console);
return console;
}
REGISTER_SIM_OBJECT("SimConsole", SimConsole)
////////////////////////////////////////////////////////////////////////
//
//
ConsoleListener::ConsoleListener(const string &name)
: SimObject(name), event(NULL)
{}
ConsoleListener::~ConsoleListener()
{
if (event)
delete event;
}
void
ConsoleListener::Event::process(int revent)
{
listener->accept();
}
///////////////////////////////////////////////////////////////////////
// socket creation and console attach
//
void
ConsoleListener::listen(int port)
{
while (!listener.listen(port, true)) {
DPRINTF(Console,
": can't bind address console port %d inuse PID %d\n",
port, getpid());
port++;
}
ccprintf(cerr, "Listening for console connection on port %d\n", port);
event = new Event(this, listener.getfd(), POLLIN);
pollQueue.schedule(event);
}
void
ConsoleListener::add(SimConsole *cons)
{ ConsoleList.push_back(cons);}
void
ConsoleListener::accept()
{
if (!listener.islistening())
panic("%s: cannot accept a connection if not listening!", name());
int sfd = listener.accept(true);
if (sfd != -1) {
iter_t i = ConsoleList.begin();
iter_t end = ConsoleList.end();
if (i == end) {
close(sfd);
} else {
(*i)->attach(sfd, this);
i = ConsoleList.erase(i);
}
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
Param<int> port;
END_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
BEGIN_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
INIT_PARAM_DFLT(port, "listen port", 3456)
END_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
CREATE_SIM_OBJECT(ConsoleListener)
{
ConsoleListener *listener = new ConsoleListener(getInstanceName());
listener->listen(port);
return listener;
}
REGISTER_SIM_OBJECT("ConsoleListener", ConsoleListener)