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gem5/tests/configs
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Sascha Bischoff e940bac278 mem: Auto-generate CommMonitor trace file names 
Splits the CommMonitor trace_file parameter into three parameters. Previously,
the trace was only enabled if the trace_file parameter was set, and would be
written to this file. This patch adds in a trace_enable and trace_compress
parameter to the CommMonitor.

No trace is generated if trace_enable is set to False. If it is set to True, the
trace is written to a file based on the name of the SimObject in the simulation
hierarchy. For example, system.cluster.il1_commmonitor.trc. This filename can be
overridden by additionally specifying a file name to the trace_file parameter
(more on this later).

The trace_compress parameter will append .gz to any filename if set to True.
This enables compression of the generated traces. If the file name already ends
in .gz, then no changes are made.

The trace_file parameter will override the name set by the trace_enable
parameter. In the case that the specified name does not end in .gz but
trace_compress is set to true, .gz is appended to the supplied file name.
2014-05-09 18:58:46 -04:00
..
alpha_generic.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
arm_generic.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
base_config.py mem: Change AbstractMemory defaults to match the common case 2013-08-19 03:52:33 -04:00
inorder-timing.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
memtest-ruby.py config: ruby: rename _cpu_ruby_ports to _cpu_ports 2014-03-20 09:14:14 -05:00
memtest.py power: Add voltage domains to the clock domains 2013-08-19 03:52:28 -04:00
o3-timing-checker.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
o3-timing-mp-ruby.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
o3-timing-mp.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
o3-timing-ruby.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
o3-timing.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
pc-o3-timing.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
pc-simple-atomic.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
pc-simple-timing-ruby.py config: ruby: rename _cpu_ruby_ports to _cpu_ports 2014-03-20 09:14:14 -05:00
pc-simple-timing.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
pc-switcheroo-full.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-o3-checker.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-o3-dual.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-o3.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-simple-atomic-dual.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
realview-simple-atomic.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
realview-simple-timing-dual.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-simple-timing.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-switcheroo-atomic.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
realview-switcheroo-full.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-switcheroo-o3.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
realview-switcheroo-timing.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
rubytest-ruby.py config: ruby: rename _cpu_ruby_ports to _cpu_ports 2014-03-20 09:14:14 -05:00
simple-atomic-dummychecker.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
simple-atomic-mp-ruby.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
simple-atomic-mp.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
simple-atomic.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
simple-timing-mp-ruby.py config: ruby: rename _cpu_ruby_ports to _cpu_ports 2014-03-20 09:14:14 -05:00
simple-timing-mp.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
simple-timing-ruby.py config: ruby: rename _cpu_ruby_ports to _cpu_ports 2014-03-20 09:14:14 -05:00
simple-timing.py config: Add a BaseSESystem builder for re-use in regressions 2013-06-27 05:49:49 -04:00
switcheroo.py tests: suppress output on switcheroo tests 2013-11-14 15:03:42 -08:00
t1000-simple-atomic.py mem: Change AbstractMemory defaults to match the common case 2013-08-19 03:52:33 -04:00
tgen-simple-dram.py power: Add voltage domains to the clock domains 2013-08-19 03:52:28 -04:00
tgen-simple-mem.py mem: Auto-generate CommMonitor trace file names 2014-05-09 18:58:46 -04:00
tsunami-inorder.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
tsunami-o3-dual.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
tsunami-o3.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
tsunami-simple-atomic-dual.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
tsunami-simple-atomic.py test: Use SimpleMemory for atomic full-system tests 2013-11-01 11:56:14 -04:00
tsunami-simple-timing-dual.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
tsunami-simple-timing.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
tsunami-switcheroo-full.py config: Move the memory instantiation outside FSConfig 2013-08-19 03:52:27 -04:00
twosys-tsunami-simple-atomic.py power: Add voltage domains to the clock domains 2013-08-19 03:52:28 -04:00
x86_generic.py config, x86: move kernel specification from tests to FSConfig.py 2014-01-03 17:08:44 -08:00