1716749c8c
The o3 pipeline interlock/stall logic is incorrect. o3 unnecessicarily stalled fetch and decode due to later stages in the pipeline. In general, a stage should usually only consider if it is stalled by the adjacent, downstream stage. Forcing stalls due to later stages creates and results in bubbles in the pipeline. Additionally, o3 stalled the entire frontend (fetch, decode, rename) on a branch mispredict while the ROB is being serially walked to update the RAT (robSquashing). Only should have stalled at rename.
321 lines
11 KiB
C++
321 lines
11 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_DECODE_HH__
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#define __CPU_O3_DECODE_HH__
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#include <queue>
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#include "base/statistics.hh"
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#include "cpu/timebuf.hh"
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struct DerivO3CPUParams;
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/**
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* DefaultDecode class handles both single threaded and SMT
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* decode. Its width is specified by the parameters; each cycles it
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* tries to decode that many instructions. Because instructions are
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* actually decoded when the StaticInst is created, this stage does
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* not do much other than check any PC-relative branches.
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*/
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template<class Impl>
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class DefaultDecode
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{
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private:
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// Typedefs from the Impl.
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typedef typename Impl::O3CPU O3CPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUPol CPUPol;
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// Typedefs from the CPU policy.
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::DecodeStruct DecodeStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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public:
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/** Overall decode stage status. Used to determine if the CPU can
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* deschedule itself due to a lack of activity.
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*/
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enum DecodeStatus {
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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StartSquash,
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Squashing,
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Blocked,
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Unblocking
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};
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private:
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/** Decode status. */
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DecodeStatus _status;
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/** Per-thread status. */
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ThreadStatus decodeStatus[Impl::MaxThreads];
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public:
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/** DefaultDecode constructor. */
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DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
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void startupStage();
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void resetStage();
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/** Returns the name of decode. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets the main backwards communication time buffer pointer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Sets pointer to time buffer used to communicate to the next stage. */
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void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
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/** Sets pointer to time buffer coming from fetch. */
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/** Has the stage drained? */
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bool isDrained() const;
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/** Takes over from another CPU's thread. */
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void takeOverFrom() { resetStage(); }
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/** Ticks decode, processing all input signals and decoding as many
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* instructions as possible.
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*/
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void tick();
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/** Determines what to do based on decode's current status.
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* @param status_change decode() sets this variable if there was a status
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* change (ie switching from from blocking to unblocking).
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* @param tid Thread id to decode instructions from.
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*/
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void decode(bool &status_change, ThreadID tid);
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/** Processes instructions from fetch and passes them on to rename.
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* Decoding of instructions actually happens when they are created in
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* fetch, so this function mostly checks if PC-relative branches are
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* correct.
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*/
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void decodeInsts(ThreadID tid);
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private:
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/** Inserts a thread's instructions into the skid buffer, to be decoded
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* once decode unblocks.
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*/
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void skidInsert(ThreadID tid);
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/** Returns if all of the skid buffers are empty. */
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bool skidsEmpty();
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/** Updates overall decode status based on all of the threads' statuses. */
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void updateStatus();
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/** Separates instructions from fetch into individual lists of instructions
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* sorted by thread.
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*/
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void sortInsts();
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/** Reads all stall signals from the backwards communication timebuffer. */
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void readStallSignals(ThreadID tid);
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/** Checks all input signals and updates decode's status appropriately. */
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bool checkSignalsAndUpdate(ThreadID tid);
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/** Checks all stall signals, and returns if any are true. */
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bool checkStall(ThreadID tid) const;
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/** Returns if there any instructions from fetch on this cycle. */
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inline bool fetchInstsValid();
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/** Switches decode to blocking, and signals back that decode has
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* become blocked.
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* @return Returns true if there is a status change.
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*/
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bool block(ThreadID tid);
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/** Switches decode to unblocking if the skid buffer is empty, and
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* signals back that decode has unblocked.
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* @return Returns true if there is a status change.
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*/
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bool unblock(ThreadID tid);
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/** Squashes if there is a PC-relative branch that was predicted
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* incorrectly. Sends squash information back to fetch.
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*/
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void squash(DynInstPtr &inst, ThreadID tid);
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public:
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/** Squashes due to commit signalling a squash. Changes status to
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* squashing and clears block/unblock signals as needed.
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*/
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unsigned squash(ThreadID tid);
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private:
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// Interfaces to objects outside of decode.
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/** CPU interface. */
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O3CPU *cpu;
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get rename's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromRename;
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/** Wire to get iew's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write information heading to previous stages. */
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// Might not be the best name as not only fetch will read it.
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typename TimeBuffer<TimeStruct>::wire toFetch;
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/** Decode instruction queue. */
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TimeBuffer<DecodeStruct> *decodeQueue;
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/** Wire used to write any information heading to rename. */
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typename TimeBuffer<DecodeStruct>::wire toRename;
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/** Fetch instruction queue interface. */
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TimeBuffer<FetchStruct> *fetchQueue;
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/** Wire to get fetch's output from fetch queue. */
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typename TimeBuffer<FetchStruct>::wire fromFetch;
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/** Queue of all instructions coming from fetch this cycle. */
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std::queue<DynInstPtr> insts[Impl::MaxThreads];
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/** Skid buffer between fetch and decode. */
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std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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/** Variable that tracks if decode has written to the time buffer this
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* cycle. Used to tell CPU if there is activity this cycle.
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*/
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bool wroteToTimeBuffer;
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/** Source of possible stalls. */
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struct Stalls {
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bool rename;
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};
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/** Tracks which stages are telling decode to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** Rename to decode delay. */
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Cycles renameToDecodeDelay;
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/** IEW to decode delay. */
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Cycles iewToDecodeDelay;
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/** Commit to decode delay. */
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Cycles commitToDecodeDelay;
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/** Fetch to decode delay. */
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Cycles fetchToDecodeDelay;
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/** The width of decode, in instructions. */
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unsigned decodeWidth;
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/** Index of instructions being sent to rename. */
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unsigned toRenameIndex;
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/** number of Active Threads*/
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ThreadID numThreads;
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/** List of active thread ids */
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std::list<ThreadID> *activeThreads;
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/** Maximum size of the skid buffer. */
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unsigned skidBufferMax;
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/** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
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Addr bdelayDoneSeqNum[Impl::MaxThreads];
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/** Instruction used for squashing branch (used for MIPS)*/
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DynInstPtr squashInst[Impl::MaxThreads];
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/** Tells when their is a pending delay slot inst. to send
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* to rename. If there is, then wait squash after the next
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* instruction (used for MIPS).
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*/
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bool squashAfterDelaySlot[Impl::MaxThreads];
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/** Stat for total number of idle cycles. */
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Stats::Scalar decodeIdleCycles;
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/** Stat for total number of blocked cycles. */
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Stats::Scalar decodeBlockedCycles;
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/** Stat for total number of normal running cycles. */
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Stats::Scalar decodeRunCycles;
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/** Stat for total number of unblocking cycles. */
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Stats::Scalar decodeUnblockCycles;
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/** Stat for total number of squashing cycles. */
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Stats::Scalar decodeSquashCycles;
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/** Stat for number of times a branch is resolved at decode. */
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Stats::Scalar decodeBranchResolved;
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/** Stat for number of times a branch mispredict is detected. */
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Stats::Scalar decodeBranchMispred;
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/** Stat for number of times decode detected a non-control instruction
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* incorrectly predicted as a branch.
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*/
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Stats::Scalar decodeControlMispred;
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/** Stat for total number of decoded instructions. */
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Stats::Scalar decodeDecodedInsts;
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/** Stat for total number of squashed instructions. */
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Stats::Scalar decodeSquashedInsts;
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};
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#endif // __CPU_O3_DECODE_HH__
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