805b9cf1d5
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet
arch/mips/faults.cc:
more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
change back to original way
base/loader/elf_object.hh:
change back to original!
--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
131 lines
4.3 KiB
C++
131 lines
4.3 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/mips/faults.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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namespace MipsISA
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{
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FaultName MachineCheckFault::_name = "Machine Check";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "Alignment";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_count;
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName PalFault::_name = "pal";
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FaultVect PalFault::_vect = 0x2001;
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FaultStat PalFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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#if FULL_SYSTEM
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void MipsFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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countStat()++;
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// exception restart address
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if (setRestartAddress() || !xc->inPalMode())
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xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
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if (skipFaultingInstruction()) {
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// traps... skip faulting instruction.
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xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
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xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
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}
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xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
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xc->setNextPC(xc->readPC() + sizeof(MachInst));
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}
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void ArithmeticFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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panic("Arithmetic traps are unimplemented!");
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}
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#endif
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} // namespace MipsISA
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