Gabe Black 5c48a05813 Merge zizzer.eecs.umich.edu:/bk/newmem ... into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge --HG-- extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d		2007-06-19 18:54:40 -07:00
..
formats	Merge zizzer.eecs.umich.edu:/bk/newmem	2007-06-19 18:54:40 -07:00
base.isa	Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles.	2007-04-11 12:25:00 +00:00
bitfields.isa	add pseduo instruction support for sparc	2007-02-21 21:06:17 -05:00
decoder.isa	The syntax used for twin stores was confusing the parser so it's now broken down farther.	2007-03-17 21:23:03 -04:00
includes.isa	create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99	2007-04-21 17:50:47 -04:00
main.isa	Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.	2006-10-23 07:55:52 -04:00
operands.isa	Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.	2007-04-22 17:43:45 +00:00