3ed048e4f5
Identifying response vnets versus other vnets will allow garnet to determine which vnets will carry data packets, and which will carry ctrl packets, and use appropriate buffer sizes (since data packets are larger than ctrl packets). This in turn allows the orion power model to accurately estimate buffer power.
1095 lines
37 KiB
Text
1095 lines
37 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
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*
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*/
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machine(L2Cache, "MESI Directory L2 Cache CMP")
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: CacheMemory * L2cacheMemory,
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int l2_request_latency = 2,
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int l2_response_latency = 2,
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int to_l1_latency = 1
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{
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// L2 BANK QUEUES
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// From local bank of L2 cache TO the network
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MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; // this L2 bank -> Memory
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MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; // this L2 bank -> a local L1
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MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory
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// FROM the network to this local bank of L2 cache
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MessageBuffer unblockToL2Cache, network="From", virtual_network="2", ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
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MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; // a local L1 -> this L2 bank
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MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank
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// MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
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// STATES
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state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
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// Base states
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NP, AccessPermission:Invalid, desc="Not present in either cache";
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SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
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M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
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MT, AccessPermission:Invalid, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
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// L2 replacement
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M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
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MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
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MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
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I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
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S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
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// Transient States for fetching data from memory
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ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
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IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
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IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
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// Blocking states
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SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
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MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
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M_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from M";
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MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
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MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
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MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
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}
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// EVENTS
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enumeration(Event, desc="L2 Cache events") {
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// L2 events
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// events initiated by the local L1s
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L1_GET_INSTR, desc="a L1I GET INSTR request for a block maped to us";
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L1_GETS, desc="a L1D GETS request for a block maped to us";
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L1_GETX, desc="a L1D GETX request for a block maped to us";
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L1_UPGRADE, desc="a L1D GETX request for a block maped to us";
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L1_PUTX, desc="L1 replacing data";
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L1_PUTX_old, desc="L1 replacing data, but no longer sharer";
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Fwd_L1_GETX, desc="L1 did not have data, so we supply";
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Fwd_L1_GETS, desc="L1 did not have data, so we supply";
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Fwd_L1_GET_INSTR, desc="L1 did not have data, so we supply";
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// events initiated by this L2
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L2_Replacement, desc="L2 Replacement", format="!r";
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L2_Replacement_clean, desc="L2 Replacement, but data is clean", format="!r";
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// events from memory controller
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Mem_Data, desc="data from memory", format="!r";
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Mem_Ack, desc="ack from memory", format="!r";
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// M->S data writeback
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WB_Data, desc="data from L1";
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WB_Data_clean, desc="clean data from L1";
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Ack, desc="writeback ack";
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Ack_all, desc="writeback ack";
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Unblock, desc="Unblock from L1 requestor";
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Unblock_Cancel, desc="Unblock from L1 requestor (FOR XACT MEMORY)";
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Exclusive_Unblock, desc="Unblock from L1 requestor";
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MEM_Inv, desc="Invalidation from directory";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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NetDest Sharers, desc="tracks the L1 shares on-chip";
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MachineID Exclusive, desc="Exclusive holder of block";
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DataBlock DataBlk, desc="data for the block";
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bool Dirty, default="false", desc="data is dirty";
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}
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// TBE fields
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structure(TBE, desc="...") {
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Address Address, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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bool Dirty, default="false", desc="Data is Dirty";
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NetDest L1_GetS_IDs, desc="Set of the internal processors that want the block in shared state";
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MachineID L1_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
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bool isPrefetch, desc="Set if this was caused by a prefetch";
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int pendingAcks, desc="number of pending acks for invalidates during writeback";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
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void set_cache_entry(AbstractCacheEntry a);
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void unset_cache_entry();
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void set_tbe(TBE a);
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void unset_tbe();
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// inclusive cache, returns L2 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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return static_cast(Entry, "pointer", L2cacheMemory[addr]);
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}
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std::string getCoherenceRequestTypeStr(CoherenceRequestType type) {
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return CoherenceRequestType_to_string(type);
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}
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bool isOneSharerLeft(Address addr, MachineID requestor, Entry cache_entry) {
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assert(is_valid(cache_entry));
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assert(cache_entry.Sharers.isElement(requestor));
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return (cache_entry.Sharers.count() == 1);
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}
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bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
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if (is_valid(cache_entry)) {
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return cache_entry.Sharers.isElement(requestor);
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} else {
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return false;
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}
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}
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void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
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assert(is_valid(cache_entry));
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DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
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machineID, requestor, addr);
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cache_entry.Sharers.add(requestor);
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:NP;
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}
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std::string getStateStr(TBE tbe, Entry cache_entry, Address addr) {
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return L2Cache_State_to_string(getState(tbe, cache_entry, addr));
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}
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// when is this called
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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// MUST CHANGE
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
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MachineID requestor, Entry cache_entry) {
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if(type == CoherenceRequestType:GETS) {
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return Event:L1_GETS;
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} else if(type == CoherenceRequestType:GET_INSTR) {
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return Event:L1_GET_INSTR;
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} else if (type == CoherenceRequestType:GETX) {
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return Event:L1_GETX;
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} else if (type == CoherenceRequestType:UPGRADE) {
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if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
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return Event:L1_UPGRADE;
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} else {
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return Event:L1_GETX;
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}
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} else if (type == CoherenceRequestType:PUTX) {
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if (isSharer(addr, requestor, cache_entry)) {
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return Event:L1_PUTX;
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} else {
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return Event:L1_PUTX_old;
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}
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} else {
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DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
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error("Invalid L1 forwarded request type");
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}
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}
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int getPendingAcks(TBE tbe) {
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return tbe.pendingAcks;
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}
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bool isDirty(Entry cache_entry) {
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assert(is_valid(cache_entry));
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return cache_entry.Dirty;
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}
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// ** OUT_PORTS **
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out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache);
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out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache);
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out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache);
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in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache) {
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if(L1unblockNetwork_in.isReady()) {
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peek(L1unblockNetwork_in, ResponseMsg) {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L2_TBEs[in_msg.Address];
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DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
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in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
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in_msg.Sender, in_msg.Type, in_msg.Destination);
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assert(in_msg.Destination.isElement(machineID));
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if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
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trigger(Event:Exclusive_Unblock, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
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trigger(Event:Unblock, in_msg.Address, cache_entry, tbe);
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} else {
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error("unknown unblock message");
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}
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}
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}
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}
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// Response IntraChip L2 Network - response msg to this particular L2 bank
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in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache) {
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if (responseIntraChipL2Network_in.isReady()) {
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peek(responseIntraChipL2Network_in, ResponseMsg) {
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// test wether it's from a local L1 or an off chip source
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L2_TBEs[in_msg.Address];
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if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
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if(in_msg.Type == CoherenceResponseType:DATA) {
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if (in_msg.Dirty) {
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trigger(Event:WB_Data, in_msg.Address, cache_entry, tbe);
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} else {
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trigger(Event:WB_Data_clean, in_msg.Address, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceResponseType:ACK) {
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if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
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trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
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} else {
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trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
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}
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} else {
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error("unknown message type");
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}
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} else { // external message
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if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
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// L2 now has data and all off-chip acks
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trigger(Event:Mem_Data, in_msg.Address, cache_entry, tbe);
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} else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
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// L2 now has data and all off-chip acks
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trigger(Event:Mem_Ack, in_msg.Address, cache_entry, tbe);
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} else if(in_msg.Type == CoherenceResponseType:INV) {
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// L2 now has data and all off-chip acks
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trigger(Event:MEM_Inv, in_msg.Address, cache_entry, tbe);
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} else {
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error("unknown message type");
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}
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}
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}
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} // if not ready, do nothing
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}
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// L1 Request
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in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache) {
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if(L1RequestIntraChipL2Network_in.isReady()) {
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peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L2_TBEs[in_msg.Address];
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DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
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in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
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in_msg.Requestor, in_msg.Type, in_msg.Destination);
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assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
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assert(in_msg.Destination.isElement(machineID));
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if (is_valid(cache_entry)) {
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// The L2 contains the block, so proceeded with handling the request
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trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
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in_msg.Requestor, cache_entry),
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in_msg.Address, cache_entry, tbe);
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} else {
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if (L2cacheMemory.cacheAvail(in_msg.Address)) {
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// L2 does't have the line, but we have space for it in the L2
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trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
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in_msg.Requestor, cache_entry),
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in_msg.Address, cache_entry, tbe);
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} else {
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// No room in the L2, so we need to make room before handling the request
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Entry L2cache_entry := getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address));
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if (isDirty(L2cache_entry)) {
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
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} else {
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trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
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}
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}
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}
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}
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}
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}
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// ACTIONS
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action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
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peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Control;
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}
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}
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}
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action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
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|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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|
enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
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assert(is_valid(cache_entry));
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|
out_msg.Address := address;
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|
out_msg.Type := in_msg.Type;
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|
out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(cache_entry.Exclusive);
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out_msg.MessageSize := MessageSizeType:Request_Control;
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}
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}
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}
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action(c_exclusiveReplacement, "c", desc="Send data to memory") {
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enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
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assert(is_valid(cache_entry));
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:ACK;
|
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out_msg.Sender := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
|
|
out_msg.AckCount := 0 - cache_entry.Sharers.count();
|
|
if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
|
|
out_msg.AckCount := out_msg.AckCount + 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
|
|
out_msg.AckCount := 0 - cache_entry.Sharers.count();
|
|
if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
|
|
out_msg.AckCount := out_msg.AckCount + 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.AckCount := 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
|
|
assert(is_valid(tbe));
|
|
assert(tbe.L1_GetS_IDs.count() > 0);
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
|
|
assert(is_valid(tbe));
|
|
assert(tbe.L1_GetS_IDs.count() == 1);
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
|
|
assert(is_valid(tbe));
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(tbe.L1_GetX_ID);
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
|
|
out_msg.Address, out_msg.Destination, out_msg.DataBlk);
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
|
|
enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:INV;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination := cache_entry.Sharers;
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
}
|
|
}
|
|
|
|
action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:INV;
|
|
out_msg.Requestor := in_msg.Requestor;
|
|
out_msg.Destination := cache_entry.Sharers;
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:INV;
|
|
out_msg.Requestor := in_msg.Requestor;
|
|
out_msg.Destination := cache_entry.Sharers;
|
|
out_msg.Destination.remove(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
// OTHER ACTIONS
|
|
action(i_allocateTBE, "i", desc="Allocate TBE for internal/external request(isPrefetch=0, number of invalidates=0)") {
|
|
check_allocate(L2_TBEs);
|
|
assert(is_valid(cache_entry));
|
|
L2_TBEs.allocate(address);
|
|
set_tbe(L2_TBEs[address]);
|
|
tbe.L1_GetS_IDs.clear();
|
|
tbe.DataBlk := cache_entry.DataBlk;
|
|
tbe.Dirty := cache_entry.Dirty;
|
|
tbe.pendingAcks := cache_entry.Sharers.count();
|
|
}
|
|
|
|
action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
|
|
L2_TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
|
|
profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles());
|
|
}
|
|
|
|
action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
|
|
profileMsgDelay(0, L1unblockNetwork_in.dequeue_getDelayCycles());
|
|
}
|
|
|
|
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
|
|
profileMsgDelay(3, responseIntraChipL2Network_in.dequeue_getDelayCycles());
|
|
}
|
|
|
|
action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
|
|
peek(responseIntraChipL2Network_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(q_updateAck, "q", desc="update pending ack count") {
|
|
peek(responseIntraChipL2Network_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
|
|
APPEND_TRANSITION_COMMENT(in_msg.AckCount);
|
|
APPEND_TRANSITION_COMMENT(" p: ");
|
|
APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
|
|
}
|
|
}
|
|
|
|
action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
|
|
peek(responseIntraChipL2Network_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.DataBlk := in_msg.DataBlk;
|
|
tbe.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(z_stall, "z", desc="Stall") {
|
|
}
|
|
|
|
action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.L1_GetS_IDs.add(in_msg.Requestor);
|
|
}
|
|
}
|
|
|
|
action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.L1_GetX_ID := in_msg.Requestor;
|
|
}
|
|
}
|
|
|
|
action(set_setMRU, "\set", desc="set the MRU entry") {
|
|
L2cacheMemory.setMRU(address);
|
|
}
|
|
|
|
action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L2cacheMemory.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
|
|
L2cacheMemory.deallocate(address);
|
|
unset_cache_entry();
|
|
}
|
|
|
|
action(t_sendWBAck, "t", desc="Send writeback ACK") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:WB_ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
// upgrader doesn't get ack from itself, hence the + 1
|
|
out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
//profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor));
|
|
}
|
|
}
|
|
|
|
action(ww_profileMissNoDir, "\w", desc="Profile this transition at the L2 because Dir won't see the request") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
// profile_request(in_msg.L1CacheStateStr, getStateStr(address), "NA", getCoherenceRequestTypeStr(in_msg.Type));
|
|
}
|
|
}
|
|
|
|
action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(cache_entry));
|
|
addSharer(address, in_msg.Requestor, cache_entry);
|
|
APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
|
|
}
|
|
}
|
|
|
|
action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
|
|
peek(L1unblockNetwork_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
addSharer(address, in_msg.Sender, cache_entry);
|
|
}
|
|
}
|
|
|
|
action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.Sharers.remove(in_msg.Requestor);
|
|
}
|
|
}
|
|
|
|
action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.Sharers.clear();
|
|
}
|
|
}
|
|
|
|
action(mm_markExclusive, "\m", desc="set the exclusive owner") {
|
|
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.Sharers.clear();
|
|
cache_entry.Exclusive := in_msg.Requestor;
|
|
addSharer(address, in_msg.Requestor, cache_entry);
|
|
}
|
|
}
|
|
|
|
action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
|
|
peek(L1unblockNetwork_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.Sharers.clear();
|
|
cache_entry.Exclusive := in_msg.Sender;
|
|
addSharer(address, in_msg.Sender, cache_entry);
|
|
}
|
|
}
|
|
|
|
action(zz_recycleL1RequestQueue, "zz", desc="recycle L1 request queue") {
|
|
L1RequestIntraChipL2Network_in.recycle();
|
|
}
|
|
|
|
action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
|
|
responseIntraChipL2Network_in.recycle();
|
|
}
|
|
|
|
|
|
//*****************************************************
|
|
// TRANSITIONS
|
|
//*****************************************************
|
|
|
|
|
|
//===============================================
|
|
// BASE STATE - I
|
|
|
|
// Transitions from I (Idle)
|
|
transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, M_MB, MT_IB, MT_SB}, L1_PUTX) {
|
|
t_sendWBAck;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, M_MB, MT_IB, MT_SB}, L1_PUTX_old) {
|
|
t_sendWBAck;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition({IM, IS, ISS, SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
transition({IM, IS, ISS, SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
|
|
zn_recycleResponseNetwork;
|
|
}
|
|
|
|
transition({S_I, M_I, MT_I}, MEM_Inv) {
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
|
|
transition({SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
|
|
transition(NP, L1_GETS, ISS) {
|
|
qq_allocateL2CacheBlock;
|
|
ll_clearSharers;
|
|
nn_addSharer;
|
|
i_allocateTBE;
|
|
ss_recordGetSL1ID;
|
|
a_issueFetchToMemory;
|
|
uu_profileMiss;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(NP, L1_GET_INSTR, IS) {
|
|
qq_allocateL2CacheBlock;
|
|
ll_clearSharers;
|
|
nn_addSharer;
|
|
i_allocateTBE;
|
|
ss_recordGetSL1ID;
|
|
a_issueFetchToMemory;
|
|
uu_profileMiss;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(NP, L1_GETX, IM) {
|
|
qq_allocateL2CacheBlock;
|
|
ll_clearSharers;
|
|
// nn_addSharer;
|
|
i_allocateTBE;
|
|
xx_recordGetXL1ID;
|
|
a_issueFetchToMemory;
|
|
uu_profileMiss;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
|
|
// transitions from IS/IM
|
|
|
|
transition(ISS, Mem_Data, MT_MB) {
|
|
m_writeDataToCache;
|
|
ex_sendExclusiveDataToGetSRequestors;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IS, Mem_Data, SS) {
|
|
m_writeDataToCache;
|
|
e_sendDataToGetSRequestors;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IM, Mem_Data, MT_MB) {
|
|
m_writeDataToCache;
|
|
ee_sendDataToGetXRequestor;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
|
|
nn_addSharer;
|
|
ss_recordGetSL1ID;
|
|
uu_profileMiss;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition({IS, ISS}, L1_GETX) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
// transitions from SS
|
|
transition(SS, {L1_GETS, L1_GET_INSTR}) {
|
|
ds_sendSharedDataToRequestor;
|
|
nn_addSharer;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
|
|
transition(SS, L1_GETX, SS_MB) {
|
|
d_sendDataToRequestor;
|
|
// fw_sendFwdInvToSharers;
|
|
fwm_sendFwdInvToSharersMinusRequestor;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(SS, L1_UPGRADE, SS_MB) {
|
|
fwm_sendFwdInvToSharersMinusRequestor;
|
|
ts_sendInvAckToUpgrader;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(SS, L2_Replacement_clean, I_I) {
|
|
i_allocateTBE;
|
|
f_sendInvToSharers;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
|
|
i_allocateTBE;
|
|
f_sendInvToSharers;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
|
|
transition(M, L1_GETX, MT_MB) {
|
|
d_sendDataToRequestor;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(M, L1_GET_INSTR, SS) {
|
|
d_sendDataToRequestor;
|
|
nn_addSharer;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(M, L1_GETS, MT_MB) {
|
|
dd_sendExclusiveDataToRequestor;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(M, {L2_Replacement, MEM_Inv}, M_I) {
|
|
i_allocateTBE;
|
|
c_exclusiveReplacement;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(M, L2_Replacement_clean, M_I) {
|
|
i_allocateTBE;
|
|
c_exclusiveCleanReplacement;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
|
|
// transitions from MT
|
|
|
|
transition(MT, L1_GETX, MT_MB) {
|
|
b_forwardRequestToExclusive;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
|
|
transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
|
|
b_forwardRequestToExclusive;
|
|
uu_profileMiss;
|
|
set_setMRU;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
|
|
i_allocateTBE;
|
|
f_sendInvToSharers;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(MT, L2_Replacement_clean, MCT_I) {
|
|
i_allocateTBE;
|
|
f_sendInvToSharers;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(MT, L1_PUTX, M) {
|
|
ll_clearSharers;
|
|
mr_writeDataToCacheFromRequest;
|
|
t_sendWBAck;
|
|
jj_popL1RequestQueue;
|
|
}
|
|
|
|
|
|
// transitions from blocking states
|
|
transition(SS_MB, Unblock_Cancel, SS) {
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition(MT_MB, Unblock_Cancel, MT) {
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition(MT_IB, Unblock_Cancel, MT) {
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition(SS_MB, Exclusive_Unblock, MT) {
|
|
// update actual directory
|
|
mmu_markExclusiveFromUnblock;
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition({M_MB, MT_MB}, Exclusive_Unblock, MT) {
|
|
// update actual directory
|
|
mmu_markExclusiveFromUnblock;
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
transition(MT_IIB, Unblock, MT_IB) {
|
|
nnu_addSharerFromUnblock;
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
|
|
m_writeDataToCache;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
|
|
m_writeDataToCache;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MT_SB, Unblock, SS) {
|
|
nnu_addSharerFromUnblock;
|
|
k_popUnblockQueue;
|
|
}
|
|
|
|
// writeback states
|
|
transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
transition(I_I, Ack) {
|
|
q_updateAck;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(I_I, Ack_all, M_I) {
|
|
c_exclusiveCleanReplacement;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition({MT_I, MCT_I}, WB_Data, M_I) {
|
|
qq_writeDataToTBE;
|
|
ct_exclusiveReplacementFromTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
|
|
c_exclusiveCleanReplacement;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
// L1 never changed Dirty data
|
|
transition(MT_I, Ack_all, M_I) {
|
|
ct_exclusiveReplacementFromTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MT_I, {L1_PUTX, L1_PUTX_old}){
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
// possible race between unblock and immediate replacement
|
|
transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
|
|
zz_recycleL1RequestQueue;
|
|
}
|
|
|
|
transition(MT_I, WB_Data_clean, NP) {
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(S_I, Ack) {
|
|
q_updateAck;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(S_I, Ack_all, M_I) {
|
|
ct_exclusiveReplacementFromTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M_I, Mem_Ack, NP) {
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
}
|