arch/sparc/isa/base.isa: Added a set of abbreviations for the different condition tests. arch/sparc/isa/decoder.isa: Fixes and additions to get syscall emulation closer to working. arch/sparc/isa/formats/branch.isa: Fixed branches so that the immediate version actually uses the immediate value arch/sparc/isa/formats/integerop.isa: Compute the condition codes -before- writing to the state of the machine. arch/sparc/isa/formats/mem.isa: An attempt to fix up the output of the disassembly of loads and stores. arch/sparc/isa/formats/trap.isa: Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions. arch/sparc/isa/operands.isa: Added an R1 operand, and fixed up the numbering arch/sparc/isa_traits.hh: SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc. arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in. arch/sparc/process.cc: arch/sparc/process.hh: Fixed up how the initial stack frame is set up. arch/sparc/regfile.hh: Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Changed the syscall mechanism to pass down the syscall number directly. --HG-- extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
220 lines
6.3 KiB
Text
220 lines
6.3 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Base class for sparc instructions, and some support functions
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//
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output header {{
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union CondCodes
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{
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struct
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{
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uint8_t c:1;
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uint8_t v:1;
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uint8_t z:1;
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uint8_t n:1;
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};
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uint32_t bits;
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};
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enum CondTest
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{
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Always=0x8,
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Never=0x0,
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NotEqual=0x9,
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Equal=0x1,
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Greater=0xA,
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LessOrEqual=0x2,
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GreaterOrEqual=0xB,
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Less=0x3,
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GreaterUnsigned=0xC,
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LessOrEqualUnsigned=0x4,
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CarryClear=0xD,
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CarrySet=0x5,
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Positive=0xE,
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Negative=0x6,
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OverflowClear=0xF,
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OverflowSet=0x7
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};
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extern char * CondTestAbbrev[];
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/**
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* Base class for all SPARC static instructions.
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*/
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class SparcStaticInst : public StaticInst
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{
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protected:
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// Constructor.
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SparcStaticInst(const char *mnem,
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MachInst _machInst, OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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void printReg(std::ostream &os, int reg) const;
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};
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bool passesCondition(uint32_t codes, uint32_t condition);
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inline int64_t sign_ext(uint64_t data, int origWidth)
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{
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int shiftAmount = 64 - origWidth;
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return (((int64_t)data) << shiftAmount) >> shiftAmount;
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}
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}};
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output decoder {{
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char * CondTestAbbrev[] =
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{
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"nev", //Never
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"e", //Equal
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"le", //Less or Equal
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"l", //Less
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"leu", //Less or Equal Unsigned
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"c", //Carry set
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"n", //Negative
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"o", //Overflow set
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"a", //Always
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"ne", //Not Equal
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"g", //Greater
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"ge", //Greater or Equal
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"gu", //Greater Unsigned
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"cc", //Carry clear
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"p", //Positive
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"oc" //Overflow Clear
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};
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}};
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def template ROrImmDecode {{
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{
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return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
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: (SparcStaticInst *)(new %(class_name)s(machInst)));
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}
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}};
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let {{
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def splitOutImm(code):
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matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)')
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rOrImmMatch = matcher.search(code)
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if (rOrImmMatch == None):
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return (False, code, '', '', '')
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rString = rOrImmMatch.group("rNum")
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iString = rOrImmMatch.group("iNum")
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orig_code = code
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code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code)
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imm_code = matcher.sub('imm', orig_code)
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return (True, code, imm_code, rString, iString)
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}};
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output decoder {{
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inline void printMnemonic(std::ostream &os, const char * mnemonic)
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{
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ccprintf(os, "\t%s ", mnemonic);
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}
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void
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SparcStaticInst::printReg(std::ostream &os, int reg) const
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{
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const int MaxGlobal = 8;
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const int MaxOutput = 16;
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const int MaxLocal = 24;
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const int MaxInput = 32;
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if (reg == FramePointerReg)
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ccprintf(os, "%%fp");
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else if (reg == StackPointerReg)
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ccprintf(os, "%%sp");
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else if(reg < MaxGlobal)
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ccprintf(os, "%%g%d", reg);
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else if(reg < MaxOutput)
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ccprintf(os, "%%o%d", reg - MaxGlobal);
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else if(reg < MaxLocal)
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ccprintf(os, "%%l%d", reg - MaxOutput);
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else if(reg < MaxInput)
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ccprintf(os, "%%i%d", reg - MaxLocal);
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else {
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ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
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}
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}
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std::string SparcStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if(_numSrcRegs > 0)
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{
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1)
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{
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if(_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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bool passesCondition(uint32_t codes, uint32_t condition)
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{
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CondCodes condCodes;
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condCodes.bits = codes;
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switch(condition)
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{
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case Always:
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return true;
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case Never:
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return false;
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case NotEqual:
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return !condCodes.z;
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case Equal:
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return condCodes.z;
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case Greater:
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return !(condCodes.z | (condCodes.n ^ condCodes.v));
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case LessOrEqual:
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return condCodes.z | (condCodes.n ^ condCodes.v);
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case GreaterOrEqual:
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return !(condCodes.n ^ condCodes.v);
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case Less:
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return (condCodes.n ^ condCodes.v);
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case GreaterUnsigned:
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return !(condCodes.c | condCodes.z);
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case LessOrEqualUnsigned:
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return (condCodes.c | condCodes.z);
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case CarryClear:
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return !condCodes.c;
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case CarrySet:
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return condCodes.c;
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case Positive:
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return !condCodes.n;
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case Negative:
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return condCodes.n;
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case OverflowClear:
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return !condCodes.v;
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case OverflowSet:
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return condCodes.v;
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}
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panic("Tried testing condition nonexistant "
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"condition code %d", condition);
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}
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}};
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