77b9829f13
base/timebuf.hh:
Updated copyright.
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.hh:
cpu/o3/fetch.hh:
cpu/o3/free_list.hh:
cpu/o3/iew.hh:
cpu/o3/inst_queue.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.cc:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Updated #define to have correct path.
docs/footer.html:
Remove e-mail addr.
--HG--
extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
163 lines
4.5 KiB
C++
163 lines
4.5 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_CPU_COMM_HH__
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#define __CPU_O3_CPU_COMM_HH__
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#include <vector>
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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#include "sim/host.hh"
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// Find better place to put this typedef.
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// The impl might be the best place for this.
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typedef short int PhysRegIndex;
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template<class Impl>
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struct SimpleFetchSimpleDecode {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleDecodeSimpleRename {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleRenameSimpleIEW {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleIEWSimpleCommit {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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bool squash;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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InstSeqNum squashedSeqNum;
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};
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template<class Impl>
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struct IssueStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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struct TimeBufStruct {
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struct decodeComm {
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bool squash;
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bool stall;
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bool predIncorrect;
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uint64_t branchAddr;
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InstSeqNum doneSeqNum;
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// Might want to package this kind of branch stuff into a single
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// struct as it is used pretty frequently.
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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};
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decodeComm decodeInfo;
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// Rename can't actually tell anything to squash or send a new PC back
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// because it doesn't do anything along those lines. But maybe leave
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// these fields in here to keep the stages mostly orthagonal.
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struct renameComm {
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bool squash;
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bool stall;
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uint64_t nextPC;
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};
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renameComm renameInfo;
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struct iewComm {
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bool stall;
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// Also eventually include skid buffer space.
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unsigned freeIQEntries;
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};
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iewComm iewInfo;
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struct commitComm {
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bool squash;
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bool stall;
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unsigned freeROBEntries;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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bool robSquashing;
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// Represents the instruction that has either been retired or
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// squashed. Similar to having a single bus that broadcasts the
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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// Extra bit of information so that the LDSTQ only updates when it
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// needs to.
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bool commitIsLoad;
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// Communication specifically to the IQ to tell the IQ that it can
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// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum;
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};
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commitComm commitInfo;
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};
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#endif //__CPU_O3_CPU_COMM_HH__
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