463aa6d49d
arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
276 lines
8.4 KiB
C++
276 lines
8.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/trace.hh"
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#include "base/traceflags.hh"
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#include "cpu/o3/bpred_unit.hh"
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template<class Impl>
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TwobitBPredUnit<Impl>::TwobitBPredUnit(Params ¶ms)
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: BP(params.local_predictor_size,
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params.local_ctr_bits,
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params.instShiftAmt),
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BTB(params.BTBEntries,
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params.BTBTagSize,
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params.instShiftAmt),
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RAS(params.RASSize)
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{
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::regStats()
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{
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lookups
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.name(name() + ".BPredUnit.lookups")
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.desc("Number of BP lookups")
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;
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condPredicted
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.name(name() + ".BPredUnit.condPredicted")
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.desc("Number of conditional branches predicted")
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;
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condIncorrect
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.name(name() + ".BPredUnit.condIncorrect")
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.desc("Number of conditional branches incorrect")
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;
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BTBLookups
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.name(name() + ".BPredUnit.BTBLookups")
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.desc("Number of BTB lookups")
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;
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BTBHits
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.name(name() + ".BPredUnit.BTBHits")
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.desc("Number of BTB hits")
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;
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BTBCorrect
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.name(name() + ".BPredUnit.BTBCorrect")
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.desc("Number of correct BTB predictions (this stat may not "
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"work properly.")
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;
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usedRAS
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.name(name() + ".BPredUnit.usedRAS")
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.desc("Number of times the RAS was used.")
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;
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RASIncorrect
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.name(name() + ".BPredUnit.RASInCorrect")
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.desc("Number of incorrect RAS predictions.")
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;
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}
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template <class Impl>
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bool
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TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
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{
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// See if branch predictor predicts taken.
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// If so, get its target addr either from the BTB or the RAS.
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// Once that's done, speculatively update the predictor?
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// Save off record of branch stuff so the RAS can be fixed
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// up once it's done.
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using TheISA::MachInst;
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bool pred_taken = false;
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Addr target;
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++lookups;
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if (inst->isUncondCtrl()) {
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DPRINTF(Fetch, "BranchPred: Unconditional control.\n");
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pred_taken = true;
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} else {
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++condPredicted;
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pred_taken = BPLookup(PC);
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DPRINTF(Fetch, "BranchPred: Branch predictor predicted %i for PC %#x"
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"\n", pred_taken, inst->readPC());
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}
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PredictorHistory predict_record(inst->seqNum, PC, pred_taken);
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// Now lookup in the BTB or RAS.
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if (pred_taken) {
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if (inst->isReturn()) {
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++usedRAS;
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// If it's a function return call, then look up the address
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// in the RAS.
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target = RAS.top();
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// Record the top entry of the RAS, and its index.
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predict_record.usedRAS = true;
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predict_record.RASIndex = RAS.topIdx();
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predict_record.RASTarget = target;
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RAS.pop();
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DPRINTF(Fetch, "BranchPred: Instruction %#x is a return, RAS "
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"predicted target: %#x, RAS index: %i.\n",
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inst->readPC(), target, predict_record.RASIndex);
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} else {
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++BTBLookups;
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if (inst->isCall()) {
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RAS.push(PC+sizeof(MachInst));
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// Record that it was a call so that the top RAS entry can
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// be popped off if the speculation is incorrect.
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predict_record.wasCall = true;
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DPRINTF(Fetch, "BranchPred: Instruction %#x was a call, "
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"adding %#x to the RAS.\n",
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inst->readPC(), PC+sizeof(MachInst));
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}
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if (BTB.valid(PC)) {
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++BTBHits;
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//If it's anything else, use the BTB to get the target addr.
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target = BTB.lookup(PC);
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DPRINTF(Fetch, "BranchPred: Instruction %#x predicted target "
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"is %#x.\n", inst->readPC(), target);
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} else {
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DPRINTF(Fetch, "BranchPred: BTB doesn't have a valid entry."
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"\n");
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pred_taken = false;
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}
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}
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}
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if (pred_taken) {
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// Set the PC and the instruction's predicted target.
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PC = target;
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inst->setPredTarg(target);
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} else {
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PC = PC + sizeof(MachInst);
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inst->setPredTarg(PC);
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}
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predHist.push_front(predict_record);
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assert(!predHist.empty());
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return pred_taken;
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn)
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{
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DPRINTF(Fetch, "BranchPred: Commiting branches until sequence number "
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"%i.\n", done_sn);
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while (!predHist.empty() && predHist.back().seqNum <= done_sn) {
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assert(!predHist.empty());
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// Update the branch predictor with the correct results of branches.
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BP.update(predHist.back().PC, predHist.back().predTaken);
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predHist.pop_back();
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}
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn)
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{
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while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
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if (predHist.front().usedRAS) {
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DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
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"target: %#x.\n",
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predHist.front().RASIndex,
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predHist.front().RASTarget);
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RAS.restore(predHist.front().RASIndex,
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predHist.front().RASTarget);
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} else if (predHist.front().wasCall) {
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DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
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"to the RAS.\n");
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RAS.pop();
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}
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predHist.pop_front();
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}
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
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const Addr &corr_target,
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const bool actually_taken)
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{
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// Now that we know that a branch was mispredicted, we need to undo
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// all the branches that have been seen up until this branch and
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// fix up everything.
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++condIncorrect;
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DPRINTF(Fetch, "BranchPred: Squashing from sequence number %i, "
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"setting target to %#x.\n",
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squashed_sn, corr_target);
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while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
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if (predHist.front().usedRAS) {
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DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
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"target: %#x.\n",
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predHist.front().RASIndex,
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predHist.front().RASTarget);
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RAS.restore(predHist.front().RASIndex,
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predHist.front().RASTarget);
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} else if (predHist.front().wasCall) {
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DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
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"to the RAS.\n");
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RAS.pop();
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}
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predHist.pop_front();
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}
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predHist.front().predTaken = actually_taken;
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if (predHist.front().usedRAS) {
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++RASIncorrect;
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}
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BP.update(predHist.front().PC, actually_taken);
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BTB.update(predHist.front().PC, corr_target);
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}
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