a514bf2150
cpu/activity.cc: cpu/activity.hh: cpu/o3/alpha_cpu.hh: Updates to include comments. cpu/base_dyn_inst.cc: Remove call to thread->misspeculating(), as it's never actually misspeculating. --HG-- extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
1221 lines
34 KiB
C++
1221 lines
34 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/isa_traits.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/o3/fetch.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "mem/mem_req.hh"
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#include "sim/byteswap.hh"
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#include "sim/root.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#endif // FULL_SYSTEM
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#include <algorithm>
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using namespace std;
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template<class Impl>
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DefaultFetch<Impl>::CacheCompletionEvent::CacheCompletionEvent(MemReqPtr &_req,
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DefaultFetch *_fetch)
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: Event(&mainEventQueue, Delayed_Writeback_Pri),
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req(_req),
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fetch(_fetch)
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{
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this->setFlags(Event::AutoDelete);
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::CacheCompletionEvent::process()
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{
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fetch->processCacheCompletion(req);
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}
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template<class Impl>
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const char *
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DefaultFetch<Impl>::CacheCompletionEvent::description()
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{
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return "DefaultFetch cache completion event";
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}
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template<class Impl>
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DefaultFetch<Impl>::DefaultFetch(Params *params)
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: icacheInterface(params->icacheInterface),
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branchPred(params),
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decodeToFetchDelay(params->decodeToFetchDelay),
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renameToFetchDelay(params->renameToFetchDelay),
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iewToFetchDelay(params->iewToFetchDelay),
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commitToFetchDelay(params->commitToFetchDelay),
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fetchWidth(params->fetchWidth),
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numThreads(params->numberOfThreads),
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numFetchingThreads(params->smtNumFetchingThreads),
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interruptPending(false)
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{
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if (numThreads > Impl::MaxThreads)
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fatal("numThreads is not a valid value\n");
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DPRINTF(Fetch, "Fetch constructor called\n");
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// Set fetch stage's status to inactive.
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_status = Inactive;
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string policy = params->smtFetchPolicy;
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// Convert string to lowercase
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std::transform(policy.begin(), policy.end(), policy.begin(),
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(int(*)(int)) tolower);
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// Figure out fetch policy
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if (policy == "singlethread") {
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fetchPolicy = SingleThread;
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} else if (policy == "roundrobin") {
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fetchPolicy = RoundRobin;
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DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
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} else if (policy == "branch") {
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fetchPolicy = Branch;
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DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
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} else if (policy == "iqcount") {
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fetchPolicy = IQ;
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DPRINTF(Fetch, "Fetch policy set to IQ count\n");
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} else if (policy == "lsqcount") {
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fetchPolicy = LSQ;
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DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
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} else {
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fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
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" RoundRobin,LSQcount,IQcount}\n");
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}
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// Size of cache block.
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cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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for (int tid=0; tid < numThreads; tid++) {
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fetchStatus[tid] = Running;
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priorityList.push_back(tid);
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// Create a new memory request.
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memReq[tid] = NULL;
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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stalls[tid].decode = 0;
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stalls[tid].rename = 0;
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stalls[tid].iew = 0;
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stalls[tid].commit = 0;
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}
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// Get the size of an instruction.
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instSize = sizeof(MachInst);
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}
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template <class Impl>
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std::string
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DefaultFetch<Impl>::name() const
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{
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return cpu->name() + ".fetch";
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::regStats()
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{
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icacheStallCycles
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.name(name() + ".icacheStallCycles")
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.desc("Number of cycles fetch is stalled on an Icache miss")
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.prereq(icacheStallCycles);
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fetchedInsts
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.name(name() + ".Insts")
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.desc("Number of instructions fetch has processed")
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.prereq(fetchedInsts);
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fetchedBranches
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.name(name() + ".Branches")
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.desc("Number of branches that fetch encountered")
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.prereq(fetchedBranches);
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predictedBranches
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.name(name() + ".predictedBranches")
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.desc("Number of branches that fetch has predicted taken")
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.prereq(predictedBranches);
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fetchCycles
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.name(name() + ".Cycles")
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.desc("Number of cycles fetch has run and was not squashing or"
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" blocked")
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.prereq(fetchCycles);
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fetchSquashCycles
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.name(name() + ".SquashCycles")
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.desc("Number of cycles fetch has spent squashing")
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.prereq(fetchSquashCycles);
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fetchIdleCycles
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.name(name() + ".IdleCycles")
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.desc("Number of cycles fetch was idle")
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.prereq(fetchIdleCycles);
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fetchBlockedCycles
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.name(name() + ".BlockedCycles")
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.desc("Number of cycles fetch has spent blocked")
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.prereq(fetchBlockedCycles);
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fetchedCacheLines
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.name(name() + ".CacheLines")
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.desc("Number of cache lines fetched")
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.prereq(fetchedCacheLines);
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fetchMiscStallCycles
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.name(name() + ".MiscStallCycles")
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.desc("Number of cycles fetch has spent waiting on interrupts, or "
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"bad addresses, or out of MSHRs")
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.prereq(fetchMiscStallCycles);
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fetchIcacheSquashes
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.name(name() + ".IcacheSquashes")
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.desc("Number of outstanding Icache misses that were squashed")
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.prereq(fetchIcacheSquashes);
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fetchNisnDist
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.init(/* base value */ 0,
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/* last value */ fetchWidth,
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/* bucket size */ 1)
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.name(name() + ".rateDist")
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.desc("Number of instructions fetched each cycle (Total)")
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.flags(Stats::pdf);
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idleRate
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.name(name() + ".idleRate")
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.desc("Percent of cycles fetch was idle")
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.prereq(idleRate);
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idleRate = fetchIdleCycles * 100 / cpu->numCycles;
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branchRate
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.name(name() + ".branchRate")
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.desc("Number of branch fetches per cycle")
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.flags(Stats::total);
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branchRate = fetchedBranches / cpu->numCycles;
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fetchRate
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.name(name() + ".rate")
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.desc("Number of inst fetches per cycle")
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.flags(Stats::total);
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fetchRate = fetchedInsts / cpu->numCycles;
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branchPred.regStats();
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
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{
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DPRINTF(Fetch, "Setting the CPU pointer.\n");
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cpu = cpu_ptr;
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// Fetch needs to start fetching instructions at the very beginning,
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// so it must start up in active state.
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switchToActive();
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
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{
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DPRINTF(Fetch, "Setting the time buffer pointer.\n");
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timeBuffer = time_buffer;
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// Create wires to get information from proper places in time buffer.
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fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
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fromRename = timeBuffer->getWire(-renameToFetchDelay);
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fromIEW = timeBuffer->getWire(-iewToFetchDelay);
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fromCommit = timeBuffer->getWire(-commitToFetchDelay);
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
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{
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DPRINTF(Fetch, "Setting active threads list pointer.\n");
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activeThreads = at_ptr;
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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{
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DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
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fetchQueue = fq_ptr;
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// Create wire to write information to proper place in fetch queue.
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toDecode = fetchQueue->getWire(0);
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}
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#if 0
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template<class Impl>
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void
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DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr)
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{
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DPRINTF(Fetch, "Setting the page table pointer.\n");
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#if !FULL_SYSTEM
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pTable = pt_ptr;
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#endif
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}
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#endif
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template<class Impl>
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void
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DefaultFetch<Impl>::initStage()
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{
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// Setup PC and nextPC with initial state.
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for (int tid = 0; tid < numThreads; tid++) {
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PC[tid] = cpu->readPC(tid);
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nextPC[tid] = cpu->readNextPC(tid);
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}
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::processCacheCompletion(MemReqPtr &req)
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{
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unsigned tid = req->thread_num;
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DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
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// Only change the status if it's still waiting on the icache access
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// to return.
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if (fetchStatus[tid] != IcacheMissStall ||
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req != memReq[tid] ||
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isSwitchedOut()) {
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++fetchIcacheSquashes;
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return;
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}
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// Wake up the CPU (if it went to sleep and was waiting on this completion
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// event).
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cpu->wakeCPU();
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DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
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tid);
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switchToActive();
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// Only switch to IcacheMissComplete if we're not stalled as well.
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if (checkStall(tid)) {
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fetchStatus[tid] = Blocked;
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} else {
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fetchStatus[tid] = IcacheMissComplete;
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}
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// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
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// Reset the mem req to NULL.
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memReq[tid] = NULL;
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::switchOut()
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{
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// Fetch is ready to switch out at any time.
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switchedOut = true;
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cpu->signalSwitched();
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::doSwitchOut()
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{
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// Branch predictor needs to have its state cleared.
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branchPred.switchOut();
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::takeOverFrom()
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{
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// Reset all state
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for (int i = 0; i < Impl::MaxThreads; ++i) {
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stalls[i].decode = 0;
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stalls[i].rename = 0;
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stalls[i].iew = 0;
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stalls[i].commit = 0;
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PC[i] = cpu->readPC(i);
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nextPC[i] = cpu->readNextPC(i);
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fetchStatus[i] = Running;
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}
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numInst = 0;
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wroteToTimeBuffer = false;
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_status = Inactive;
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switchedOut = false;
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branchPred.takeOverFrom();
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::wakeFromQuiesce()
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{
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DPRINTF(Fetch, "Waking up from quiesce\n");
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// Hopefully this is safe
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// @todo: Allow other threads to wake from quiesce.
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fetchStatus[0] = Running;
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}
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template <class Impl>
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inline void
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DefaultFetch<Impl>::switchToActive()
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{
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if (_status == Inactive) {
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DPRINTF(Activity, "Activating stage.\n");
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cpu->activateStage(FullCPU::FetchIdx);
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_status = Active;
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}
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}
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template <class Impl>
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inline void
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DefaultFetch<Impl>::switchToInactive()
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{
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if (_status == Active) {
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DPRINTF(Activity, "Deactivating stage.\n");
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cpu->deactivateStage(FullCPU::FetchIdx);
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_status = Inactive;
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}
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}
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template <class Impl>
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bool
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DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
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{
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// Do branch prediction check here.
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// A bit of a misnomer...next_PC is actually the current PC until
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// this function updates it.
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bool predict_taken;
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if (!inst->isControl()) {
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next_PC = next_PC + instSize;
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inst->setPredTarg(next_PC);
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return false;
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}
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predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
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++fetchedBranches;
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if (predict_taken) {
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++predictedBranches;
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}
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return predict_taken;
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}
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template <class Impl>
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bool
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DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
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{
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Fault fault = NoFault;
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#if FULL_SYSTEM
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// Flag to say whether or not address is physical addr.
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unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
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#else
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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if (interruptPending && flags == 0 || switchedOut) {
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// Hold off fetch from getting new instructions while an interrupt
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// is pending.
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return false;
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}
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// Align the fetch PC so it's at the start of a cache block.
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fetch_PC = icacheBlockAlignPC(fetch_PC);
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// Setup the memReq to do a read of the first instruction's address.
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// Set the appropriate read size and flags as well.
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memReq[tid] = new MemReq();
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memReq[tid]->asid = tid;
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memReq[tid]->thread_num = tid;
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memReq[tid]->data = new uint8_t[64];
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memReq[tid]->xc = cpu->xcBase(tid);
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memReq[tid]->cmd = Read;
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memReq[tid]->reset(fetch_PC, cacheBlkSize, flags);
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// Translate the instruction request.
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//#if FULL_SYSTEM
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fault = cpu->translateInstReq(memReq[tid]);
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//#else
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// fault = pTable->translate(memReq[tid]);
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//#endif
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// In the case of faults, the fetch stage may need to stall and wait
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// for the ITB miss to be handled.
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// If translation was successful, attempt to read the first
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// instruction.
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if (fault == NoFault) {
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#if FULL_SYSTEM
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if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
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memReq[tid]->flags & UNCACHEABLE) {
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DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
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"misspeculating path)!",
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memReq[tid]->paddr);
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ret_fault = TheISA::genMachineCheckFault();
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return false;
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}
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#endif
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DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
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fault = cpu->mem->read(memReq[tid], cacheData[tid]);
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// This read may change when the mem interface changes.
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (icacheInterface && !icacheInterface->isBlocked()) {
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DPRINTF(Fetch, "Doing cache access.\n");
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memReq[tid]->completionEvent = NULL;
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memReq[tid]->time = curTick;
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MemAccessResult result = icacheInterface->access(memReq[tid]);
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fetchedCacheLines++;
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// If the cache missed, then schedule an event to wake
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// up this stage once the cache miss completes.
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// @todo: Possibly allow for longer than 1 cycle cache hits.
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if (result != MA_HIT && icacheInterface->doEvents()) {
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memReq[tid]->completionEvent =
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new CacheCompletionEvent(memReq[tid], this);
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lastIcacheStall[tid] = curTick;
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DPRINTF(Activity, "[tid:%i]: Activity: Stalling due to I-cache "
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"miss.\n", tid);
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fetchStatus[tid] = IcacheMissStall;
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} else {
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DPRINTF(Fetch, "[tid:%i]: I-Cache hit. Doing Instruction "
|
|
"read.\n", tid);
|
|
|
|
// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
|
|
}
|
|
} else {
|
|
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
|
|
ret_fault = NoFault;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
ret_fault = fault;
|
|
return true;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
|
|
tid, new_PC);
|
|
|
|
PC[tid] = new_PC;
|
|
nextPC[tid] = new_PC + instSize;
|
|
|
|
// Clear the icache miss if it's outstanding.
|
|
if (fetchStatus[tid] == IcacheMissStall && icacheInterface) {
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
|
|
tid);
|
|
memReq[tid] = NULL;
|
|
}
|
|
|
|
fetchStatus[tid] = Squashing;
|
|
|
|
++fetchSquashCycles;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
|
|
const InstSeqNum &seq_num,
|
|
unsigned tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
|
|
|
|
doSquash(new_PC, tid);
|
|
|
|
// Tell the CPU to remove any instructions that are in flight between
|
|
// fetch and decode.
|
|
cpu->removeInstsUntil(seq_num, tid);
|
|
}
|
|
|
|
template<class Impl>
|
|
bool
|
|
DefaultFetch<Impl>::checkStall(unsigned tid) const
|
|
{
|
|
bool ret_val = false;
|
|
|
|
if (cpu->contextSwitch) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].decode) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].rename) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].iew) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].commit) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
|
|
ret_val = true;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
template<class Impl>
|
|
typename DefaultFetch<Impl>::FetchStatus
|
|
DefaultFetch<Impl>::updateFetchStatus()
|
|
{
|
|
//Check Running
|
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
|
|
|
while (threads != (*activeThreads).end()) {
|
|
|
|
unsigned tid = *threads++;
|
|
|
|
if (fetchStatus[tid] == Running ||
|
|
fetchStatus[tid] == Squashing ||
|
|
fetchStatus[tid] == IcacheMissComplete) {
|
|
|
|
if (_status == Inactive) {
|
|
DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
|
|
|
|
if (fetchStatus[tid] == IcacheMissComplete) {
|
|
DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
|
|
"completion\n",tid);
|
|
}
|
|
|
|
cpu->activateStage(FullCPU::FetchIdx);
|
|
}
|
|
|
|
return Active;
|
|
}
|
|
}
|
|
|
|
// Stage is switching from active to inactive, notify CPU of it.
|
|
if (_status == Active) {
|
|
DPRINTF(Activity, "Deactivating stage.\n");
|
|
|
|
cpu->deactivateStage(FullCPU::FetchIdx);
|
|
}
|
|
|
|
return Inactive;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
|
|
|
|
doSquash(new_PC, tid);
|
|
|
|
// Tell the CPU to remove any instructions that are not in the ROB.
|
|
cpu->removeInstsNotInROB(tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultFetch<Impl>::tick()
|
|
{
|
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
|
bool status_change = false;
|
|
|
|
wroteToTimeBuffer = false;
|
|
|
|
while (threads != (*activeThreads).end()) {
|
|
unsigned tid = *threads++;
|
|
|
|
// Check the signals for each thread to determine the proper status
|
|
// for each thread.
|
|
bool updated_status = checkSignalsAndUpdate(tid);
|
|
status_change = status_change || updated_status;
|
|
}
|
|
|
|
DPRINTF(Fetch, "Running stage.\n");
|
|
|
|
// Reset the number of the instruction we're fetching.
|
|
numInst = 0;
|
|
|
|
if (fromCommit->commitInfo[0].interruptPending) {
|
|
interruptPending = true;
|
|
}
|
|
if (fromCommit->commitInfo[0].clearInterrupt) {
|
|
interruptPending = false;
|
|
}
|
|
|
|
for (threadFetched = 0; threadFetched < numFetchingThreads;
|
|
threadFetched++) {
|
|
// Fetch each of the actively fetching threads.
|
|
fetch(status_change);
|
|
}
|
|
|
|
// Record number of instructions fetched this cycle for distribution.
|
|
fetchNisnDist.sample(numInst);
|
|
|
|
if (status_change) {
|
|
// Change the fetch stage status if there was a status change.
|
|
_status = updateFetchStatus();
|
|
}
|
|
|
|
// If there was activity this cycle, inform the CPU of it.
|
|
if (wroteToTimeBuffer || cpu->contextSwitch) {
|
|
DPRINTF(Activity, "Activity this cycle.\n");
|
|
|
|
cpu->activityThisCycle();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|
{
|
|
// Update the per thread stall statuses.
|
|
if (fromDecode->decodeBlock[tid]) {
|
|
stalls[tid].decode = true;
|
|
}
|
|
|
|
if (fromDecode->decodeUnblock[tid]) {
|
|
assert(stalls[tid].decode);
|
|
assert(!fromDecode->decodeBlock[tid]);
|
|
stalls[tid].decode = false;
|
|
}
|
|
|
|
if (fromRename->renameBlock[tid]) {
|
|
stalls[tid].rename = true;
|
|
}
|
|
|
|
if (fromRename->renameUnblock[tid]) {
|
|
assert(stalls[tid].rename);
|
|
assert(!fromRename->renameBlock[tid]);
|
|
stalls[tid].rename = false;
|
|
}
|
|
|
|
if (fromIEW->iewBlock[tid]) {
|
|
stalls[tid].iew = true;
|
|
}
|
|
|
|
if (fromIEW->iewUnblock[tid]) {
|
|
assert(stalls[tid].iew);
|
|
assert(!fromIEW->iewBlock[tid]);
|
|
stalls[tid].iew = false;
|
|
}
|
|
|
|
if (fromCommit->commitBlock[tid]) {
|
|
stalls[tid].commit = true;
|
|
}
|
|
|
|
if (fromCommit->commitUnblock[tid]) {
|
|
assert(stalls[tid].commit);
|
|
assert(!fromCommit->commitBlock[tid]);
|
|
stalls[tid].commit = false;
|
|
}
|
|
|
|
// Check squash signals from commit.
|
|
if (fromCommit->commitInfo[tid].squash) {
|
|
|
|
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
|
|
"from commit.\n",tid);
|
|
|
|
// In any case, squash.
|
|
squash(fromCommit->commitInfo[tid].nextPC,tid);
|
|
|
|
// Also check if there's a mispredict that happened.
|
|
if (fromCommit->commitInfo[tid].branchMispredict) {
|
|
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
|
|
fromCommit->commitInfo[tid].nextPC,
|
|
fromCommit->commitInfo[tid].branchTaken,
|
|
tid);
|
|
} else {
|
|
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
|
|
tid);
|
|
}
|
|
|
|
return true;
|
|
} else if (fromCommit->commitInfo[tid].doneSeqNum) {
|
|
// Update the branch predictor if it wasn't a squashed instruction
|
|
// that was broadcasted.
|
|
branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
|
|
}
|
|
|
|
// Check ROB squash signals from commit.
|
|
if (fromCommit->commitInfo[tid].robSquashing) {
|
|
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid);
|
|
|
|
// Continue to squash.
|
|
fetchStatus[tid] = Squashing;
|
|
|
|
return true;
|
|
}
|
|
|
|
// Check squash signals from decode.
|
|
if (fromDecode->decodeInfo[tid].squash) {
|
|
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
|
|
"from decode.\n",tid);
|
|
|
|
// Update the branch predictor.
|
|
if (fromDecode->decodeInfo[tid].branchMispredict) {
|
|
branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
|
|
fromDecode->decodeInfo[tid].nextPC,
|
|
fromDecode->decodeInfo[tid].branchTaken,
|
|
tid);
|
|
} else {
|
|
branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
|
|
tid);
|
|
}
|
|
|
|
if (fetchStatus[tid] != Squashing) {
|
|
// Squash unless we're already squashing
|
|
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
|
|
fromDecode->decodeInfo[tid].doneSeqNum,
|
|
tid);
|
|
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (fetchStatus[tid] != IcacheMissStall && checkStall(tid)) {
|
|
DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
|
|
|
|
fetchStatus[tid] = Blocked;
|
|
|
|
return true;
|
|
}
|
|
|
|
if (fetchStatus[tid] == Blocked ||
|
|
fetchStatus[tid] == Squashing) {
|
|
// Switch status to running if fetch isn't being told to block or
|
|
// squash this cycle.
|
|
DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
|
|
tid);
|
|
|
|
fetchStatus[tid] = Running;
|
|
|
|
return true;
|
|
}
|
|
|
|
// If we've reached this point, we have not gotten any signals that
|
|
// cause fetch to change its status. Fetch remains the same as before.
|
|
return false;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultFetch<Impl>::fetch(bool &status_change)
|
|
{
|
|
//////////////////////////////////////////
|
|
// Start actual fetch
|
|
//////////////////////////////////////////
|
|
int tid = getFetchingThread(fetchPolicy);
|
|
|
|
if (tid == -1) {
|
|
DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
|
|
|
|
// Breaks looping condition in tick()
|
|
threadFetched = numFetchingThreads;
|
|
return;
|
|
}
|
|
|
|
// The current PC.
|
|
Addr &fetch_PC = PC[tid];
|
|
|
|
// Fault code for memory access.
|
|
Fault fault = NoFault;
|
|
|
|
// If returning from the delay of a cache miss, then update the status
|
|
// to running, otherwise do the cache access. Possibly move this up
|
|
// to tick() function.
|
|
if (fetchStatus[tid] == IcacheMissComplete) {
|
|
DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
|
|
tid);
|
|
|
|
fetchStatus[tid] = Running;
|
|
status_change = true;
|
|
} else if (fetchStatus[tid] == Running) {
|
|
DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
|
|
"instruction, starting at PC %08p.\n",
|
|
tid, fetch_PC);
|
|
|
|
bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
|
|
if (!fetch_success) {
|
|
++fetchMiscStallCycles;
|
|
return;
|
|
}
|
|
} else {
|
|
if (fetchStatus[tid] == Idle) {
|
|
++fetchIdleCycles;
|
|
} else if (fetchStatus[tid] == Blocked) {
|
|
++fetchBlockedCycles;
|
|
} else if (fetchStatus[tid] == Squashing) {
|
|
++fetchSquashCycles;
|
|
} else if (fetchStatus[tid] == IcacheMissStall) {
|
|
++icacheStallCycles;
|
|
}
|
|
|
|
// Status is Idle, Squashing, Blocked, or IcacheMissStall, so
|
|
// fetch should do nothing.
|
|
return;
|
|
}
|
|
|
|
++fetchCycles;
|
|
|
|
// If we had a stall due to an icache miss, then return.
|
|
if (fetchStatus[tid] == IcacheMissStall) {
|
|
++icacheStallCycles;
|
|
status_change = true;
|
|
return;
|
|
}
|
|
|
|
Addr next_PC = fetch_PC;
|
|
InstSeqNum inst_seq;
|
|
MachInst inst;
|
|
ExtMachInst ext_inst;
|
|
// @todo: Fix this hack.
|
|
unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
|
|
|
|
if (fault == NoFault) {
|
|
// If the read of the first instruction was successful, then grab the
|
|
// instructions from the rest of the cache line and put them into the
|
|
// queue heading to decode.
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
|
|
"decode.\n",tid);
|
|
|
|
// Need to keep track of whether or not a predicted branch
|
|
// ended this fetch block.
|
|
bool predicted_branch = false;
|
|
|
|
for (;
|
|
offset < cacheBlkSize &&
|
|
numInst < fetchWidth &&
|
|
!predicted_branch;
|
|
++numInst) {
|
|
|
|
// Get a sequence number.
|
|
inst_seq = cpu->getAndIncrementInstSeq();
|
|
|
|
// Make sure this is a valid index.
|
|
assert(offset <= cacheBlkSize - instSize);
|
|
|
|
// Get the instruction from the array of the cache line.
|
|
inst = gtoh(*reinterpret_cast<MachInst *>
|
|
(&cacheData[tid][offset]));
|
|
|
|
ext_inst = TheISA::makeExtMI(inst, fetch_PC);
|
|
|
|
// Create a new DynInst from the instruction fetched.
|
|
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
|
|
next_PC,
|
|
inst_seq, cpu);
|
|
instruction->setThread(tid);
|
|
|
|
instruction->setASID(tid);
|
|
|
|
instruction->setState(cpu->thread[tid]);
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
|
|
"[sn:%lli]\n",
|
|
tid, instruction->readPC(), inst_seq);
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
|
|
tid, instruction->staticInst->disassemble(fetch_PC));
|
|
|
|
instruction->traceData =
|
|
Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu,
|
|
instruction->staticInst,
|
|
instruction->readPC(),tid);
|
|
|
|
predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
|
|
|
|
// Add instruction to the CPU's list of instructions.
|
|
instruction->setInstListIt(cpu->addInst(instruction));
|
|
|
|
// Write the instruction to the first slot in the queue
|
|
// that heads to decode.
|
|
toDecode->insts[numInst] = instruction;
|
|
|
|
toDecode->size++;
|
|
|
|
// Increment stat of fetched instructions.
|
|
++fetchedInsts;
|
|
|
|
// Move to the next instruction, unless we have a branch.
|
|
fetch_PC = next_PC;
|
|
|
|
if (instruction->isQuiesce()) {
|
|
warn("%lli: Quiesce instruction encountered, halting fetch!",
|
|
curTick);
|
|
fetchStatus[tid] = QuiescePending;
|
|
++numInst;
|
|
status_change = true;
|
|
break;
|
|
}
|
|
|
|
offset+= instSize;
|
|
}
|
|
}
|
|
|
|
if (numInst > 0) {
|
|
wroteToTimeBuffer = true;
|
|
}
|
|
|
|
// Now that fetching is completed, update the PC to signify what the next
|
|
// cycle will be.
|
|
if (fault == NoFault) {
|
|
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
|
|
|
|
PC[tid] = next_PC;
|
|
nextPC[tid] = next_PC + instSize;
|
|
} else {
|
|
// We shouldn't be in an icache miss and also have a fault (an ITB
|
|
// miss)
|
|
if (fetchStatus[tid] == IcacheMissStall) {
|
|
panic("Fetch should have exited prior to this!");
|
|
}
|
|
|
|
// Send the fault to commit. This thread will not do anything
|
|
// until commit handles the fault. The only other way it can
|
|
// wake up is if a squash comes along and changes the PC.
|
|
#if FULL_SYSTEM
|
|
assert(numInst != fetchWidth);
|
|
// Get a sequence number.
|
|
inst_seq = cpu->getAndIncrementInstSeq();
|
|
// We will use a nop in order to carry the fault.
|
|
ext_inst = TheISA::NoopMachInst;
|
|
|
|
// Create a new DynInst from the dummy nop.
|
|
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
|
|
next_PC,
|
|
inst_seq, cpu);
|
|
instruction->setPredTarg(next_PC + instSize);
|
|
instruction->setThread(tid);
|
|
|
|
instruction->setASID(tid);
|
|
|
|
instruction->setState(cpu->thread[tid]);
|
|
|
|
instruction->traceData = NULL;
|
|
|
|
instruction->setInstListIt(cpu->addInst(instruction));
|
|
|
|
instruction->fault = fault;
|
|
|
|
toDecode->insts[numInst] = instruction;
|
|
toDecode->size++;
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
|
|
|
|
fetchStatus[tid] = TrapPending;
|
|
status_change = true;
|
|
|
|
warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC %08p", fault, PC[tid]);
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
}
|
|
|
|
|
|
///////////////////////////////////////
|
|
// //
|
|
// SMT FETCH POLICY MAINTAINED HERE //
|
|
// //
|
|
///////////////////////////////////////
|
|
template<class Impl>
|
|
int
|
|
DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
|
|
{
|
|
if (numThreads > 1) {
|
|
switch (fetch_priority) {
|
|
|
|
case SingleThread:
|
|
return 0;
|
|
|
|
case RoundRobin:
|
|
return roundRobin();
|
|
|
|
case IQ:
|
|
return iqCount();
|
|
|
|
case LSQ:
|
|
return lsqCount();
|
|
|
|
case Branch:
|
|
return branchCount();
|
|
|
|
default:
|
|
return -1;
|
|
}
|
|
} else {
|
|
int tid = *((*activeThreads).begin());
|
|
|
|
if (fetchStatus[tid] == Running ||
|
|
fetchStatus[tid] == IcacheMissComplete ||
|
|
fetchStatus[tid] == Idle) {
|
|
return tid;
|
|
} else {
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
|
|
template<class Impl>
|
|
int
|
|
DefaultFetch<Impl>::roundRobin()
|
|
{
|
|
list<unsigned>::iterator pri_iter = priorityList.begin();
|
|
list<unsigned>::iterator end = priorityList.end();
|
|
|
|
int high_pri;
|
|
|
|
while (pri_iter != end) {
|
|
high_pri = *pri_iter;
|
|
|
|
assert(high_pri <= numThreads);
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheMissComplete ||
|
|
fetchStatus[high_pri] == Idle) {
|
|
|
|
priorityList.erase(pri_iter);
|
|
priorityList.push_back(high_pri);
|
|
|
|
return high_pri;
|
|
}
|
|
|
|
pri_iter++;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
template<class Impl>
|
|
int
|
|
DefaultFetch<Impl>::iqCount()
|
|
{
|
|
priority_queue<unsigned> PQ;
|
|
|
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
|
|
|
while (threads != (*activeThreads).end()) {
|
|
unsigned tid = *threads++;
|
|
|
|
PQ.push(fromIEW->iewInfo[tid].iqCount);
|
|
}
|
|
|
|
while (!PQ.empty()) {
|
|
|
|
unsigned high_pri = PQ.top();
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheMissComplete ||
|
|
fetchStatus[high_pri] == Idle)
|
|
return high_pri;
|
|
else
|
|
PQ.pop();
|
|
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
template<class Impl>
|
|
int
|
|
DefaultFetch<Impl>::lsqCount()
|
|
{
|
|
priority_queue<unsigned> PQ;
|
|
|
|
|
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
|
|
|
while (threads != (*activeThreads).end()) {
|
|
unsigned tid = *threads++;
|
|
|
|
PQ.push(fromIEW->iewInfo[tid].ldstqCount);
|
|
}
|
|
|
|
while (!PQ.empty()) {
|
|
|
|
unsigned high_pri = PQ.top();
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheMissComplete ||
|
|
fetchStatus[high_pri] == Idle)
|
|
return high_pri;
|
|
else
|
|
PQ.pop();
|
|
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
template<class Impl>
|
|
int
|
|
DefaultFetch<Impl>::branchCount()
|
|
{
|
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
|
|
|
return *threads;
|
|
}
|