Nilay Vaish 8ccfd9defa ruby: dma sequencer: remove RubyPort as parent class ... As of now DMASequencer inherits from the RubyPort class. But the code in RubyPort class is heavily tailored for the CPU Sequencer. There are parts of the code that are not required at all for the DMA sequencer. Moreover, the next patch uses the dma sequencer for carrying out memory accesses for all the io devices. Hence, it is better to have a leaner dma sequencer.		2014-11-06 00:55:09 -06:00
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arch	automated merge	2014-10-29 23:22:26 -05:00
base	arm: Fix multi-system AArch64 boot w/caches.	2014-10-29 23:18:26 -05:00
cpu	cpu: Add writeback modeling for drain functionality	2014-10-29 23:18:27 -05:00
dev	misc: Use gmtime for conversion to UTC to avoid getenv/setenv	2014-10-20 18:03:55 -04:00
doc	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	misc: Move AddrRangeList from port.hh to addr_range.hh	2014-10-16 05:49:59 -04:00
mem	ruby: dma sequencer: remove RubyPort as parent class	2014-11-06 00:55:09 -06:00
proto	mem: change the namespace Message to ProtoMessage	2014-09-01 16:55:46 -05:00
python	sim: EventQueue wakeup on events scheduled outside the event loop	2014-10-16 05:49:53 -04:00
sim	syscall_emul: add retry flag to SyscallReturn	2014-09-02 16:07:50 -05:00
unittest	unittest: Fix build errors	2014-01-30 12:21:58 -06:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	arch,x86,mem: Dynamically determine the ISA for Ruby store check	2014-10-16 05:49:44 -04:00