829 lines
26 KiB
C++
829 lines
26 KiB
C++
/*****************************************************************************
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* McPAT/CACTI
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <cassert>
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#include <cmath>
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#include <iostream>
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#include "basic_circuit.h"
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#include "parameter.h"
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uint32_t _log2(uint64_t num)
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{
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uint32_t log2 = 0;
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if (num == 0)
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{
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std::cerr << "log0?" << std::endl;
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exit(1);
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}
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while (num > 1)
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{
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num = (num >> 1);
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log2++;
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}
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return log2;
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}
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bool is_pow2(int64_t val)
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{
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if (val <= 0)
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{
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return false;
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}
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else if (val == 1)
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{
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return true;
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}
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else
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{
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return (_log2(val) != _log2(val-1));
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}
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}
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int powers (int base, int n)
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{
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int i, p;
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p = 1;
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for (i = 1; i <= n; ++i)
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p *= base;
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return p;
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}
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/*----------------------------------------------------------------------*/
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double logtwo (double x)
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{
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assert(x > 0);
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return ((double) (log (x) / log (2.0)));
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}
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/*----------------------------------------------------------------------*/
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double gate_C(
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double width,
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double wirelength,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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const TechnologyParameter::DeviceType * dt;
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if (_is_dram && _is_cell)
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{
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dt = &g_tp.dram_acc; //DRAM cell access transistor
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}
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else if (_is_dram && _is_wl_tr)
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{
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dt = &g_tp.dram_wl; //DRAM wordline transistor
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}
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else if (!_is_dram && _is_cell)
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{
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dt = &g_tp.sram_cell; // SRAM cell access transistor
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}
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else
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{
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dt = &g_tp.peri_global;
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}
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return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
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}
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// returns gate capacitance in Farads
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// actually this function is the same as gate_C() now
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double gate_C_pass(
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double width, // gate width in um (length is Lphy_periph_global)
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double wirelength, // poly wire length going to gate in lambda
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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// v5.0
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const TechnologyParameter::DeviceType * dt;
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if ((_is_dram) && (_is_cell))
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{
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dt = &g_tp.dram_acc; //DRAM cell access transistor
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}
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else if ((_is_dram) && (_is_wl_tr))
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{
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dt = &g_tp.dram_wl; //DRAM wordline transistor
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}
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else if ((!_is_dram) && _is_cell)
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{
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dt = &g_tp.sram_cell; // SRAM cell access transistor
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}
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else
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{
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dt = &g_tp.peri_global;
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}
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return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
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}
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double drain_C_(
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double width,
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int nchannel,
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int stack,
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int next_arg_thresh_folding_width_or_height_cell,
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double fold_dimension,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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double w_folded_tr;
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const TechnologyParameter::DeviceType * dt;
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if ((_is_dram) && (_is_cell))
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{
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dt = &g_tp.dram_acc; // DRAM cell access transistor
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}
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else if ((_is_dram) && (_is_wl_tr))
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{
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dt = &g_tp.dram_wl; // DRAM wordline transistor
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}
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else if ((!_is_dram) && _is_cell)
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{
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dt = &g_tp.sram_cell; // SRAM cell access transistor
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}
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else
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{
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dt = &g_tp.peri_global;
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}
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double c_junc_area = dt->C_junc;
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double c_junc_sidewall = dt->C_junc_sidewall;
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double c_fringe = 2*dt->C_fringe;
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double c_overlap = 2*dt->C_overlap;
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double drain_C_metal_connecting_folded_tr = 0;
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// determine the width of the transistor after folding (if it is getting folded)
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if (next_arg_thresh_folding_width_or_height_cell == 0)
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{ // interpret fold_dimension as the the folding width threshold
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// i.e. the value of transistor width above which the transistor gets folded
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w_folded_tr = fold_dimension;
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}
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else
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{ // interpret fold_dimension as the height of the cell that this transistor is part of.
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double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL;
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// TODO : w_folded_tr must come from Component::compute_gate_area()
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double ratio_p_to_n = 2.0 / (2.0 + 1.0);
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if (nchannel)
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{
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w_folded_tr = (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
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}
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else
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{
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w_folded_tr = ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
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}
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}
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int num_folded_tr = (int) (ceil(width / w_folded_tr));
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if (num_folded_tr < 2)
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{
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w_folded_tr = width;
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}
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double total_drain_w = (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + // only for drain
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(stack - 1) * g_tp.spacing_poly_to_poly;
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double drain_h_for_sidewall = w_folded_tr;
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double total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1);
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if (num_folded_tr > 1)
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{
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total_drain_w += (num_folded_tr - 2) * (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) +
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(num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly);
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if (num_folded_tr%2 == 0)
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{
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drain_h_for_sidewall = 0;
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}
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total_drain_height_for_cap_wrt_gate *= num_folded_tr;
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drain_C_metal_connecting_folded_tr = g_tp.wire_local.C_per_um * total_drain_w;
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}
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double drain_C_area = c_junc_area * total_drain_w * w_folded_tr;
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double drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w);
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double drain_C_wrt_gate = (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate;
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return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + drain_C_metal_connecting_folded_tr);
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}
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double tr_R_on(
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double width,
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int nchannel,
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int stack,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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const TechnologyParameter::DeviceType * dt;
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if ((_is_dram) && (_is_cell))
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{
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dt = &g_tp.dram_acc; //DRAM cell access transistor
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}
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else if ((_is_dram) && (_is_wl_tr))
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{
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dt = &g_tp.dram_wl; //DRAM wordline transistor
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}
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else if ((!_is_dram) && _is_cell)
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{
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dt = &g_tp.sram_cell; // SRAM cell access transistor
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}
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else
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{
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dt = &g_tp.peri_global;
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}
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double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
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return (stack * restrans / width);
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}
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/* This routine operates in reverse: given a resistance, it finds
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* the transistor width that would have this R. It is used in the
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* data wordline to estimate the wordline driver size. */
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// returns width in um
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double R_to_w(
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double res,
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int nchannel,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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const TechnologyParameter::DeviceType * dt;
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if ((_is_dram) && (_is_cell))
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{
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dt = &g_tp.dram_acc; //DRAM cell access transistor
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}
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else if ((_is_dram) && (_is_wl_tr))
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{
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dt = &g_tp.dram_wl; //DRAM wordline transistor
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}
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else if ((!_is_dram) && (_is_cell))
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{
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dt = &g_tp.sram_cell; // SRAM cell access transistor
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}
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else
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{
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dt = &g_tp.peri_global;
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}
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double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
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return (restrans / res);
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}
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double pmos_to_nmos_sz_ratio(
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bool _is_dram,
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bool _is_wl_tr)
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{
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double p_to_n_sizing_ratio;
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if ((_is_dram) && (_is_wl_tr))
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{ //DRAM wordline transistor
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p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio;
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}
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else
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{ //DRAM or SRAM all other transistors
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p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio;
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}
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return p_to_n_sizing_ratio;
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}
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// "Timing Models for MOS Circuits" by Mark Horowitz, 1984
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double horowitz(
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double inputramptime, // input rise time
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double tf, // time constant of gate
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double vs1, // threshold voltage
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double vs2, // threshold voltage
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int rise) // whether input rises or fall
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{
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if (inputramptime == 0 && vs1 == vs2)
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{
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return tf * (vs1 < 1 ? -log(vs1) : log(vs1));
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}
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double a, b, td;
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a = inputramptime / tf;
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if (rise == RISE)
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{
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b = 0.5;
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td = tf * sqrt(log(vs1)*log(vs1) + 2*a*b*(1.0 - vs1)) + tf*(log(vs1) - log(vs2));
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}
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else
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{
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b = 0.4;
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td = tf * sqrt(log(1.0 - vs1)*log(1.0 - vs1) + 2*a*b*(vs1)) + tf*(log(1.0 - vs1) - log(1.0 - vs2));
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}
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return (td);
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}
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double cmos_Ileak(
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double nWidth,
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double pWidth,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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TechnologyParameter::DeviceType * dt;
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if ((!_is_dram)&&(_is_cell))
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{ //SRAM cell access transistor
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dt = &(g_tp.sram_cell);
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}
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else if ((_is_dram)&&(_is_wl_tr))
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{ //DRAM wordline transistor
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dt = &(g_tp.dram_wl);
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}
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else
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{ //DRAM or SRAM all other transistors
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dt = &(g_tp.peri_global);
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}
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return nWidth*dt->I_off_n + pWidth*dt->I_off_p;
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}
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double simplified_nmos_leakage(
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double nwidth,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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TechnologyParameter::DeviceType * dt;
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if ((!_is_dram)&&(_is_cell))
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{ //SRAM cell access transistor
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dt = &(g_tp.sram_cell);
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}
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else if ((_is_dram)&&(_is_wl_tr))
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{ //DRAM wordline transistor
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dt = &(g_tp.dram_wl);
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}
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else
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{ //DRAM or SRAM all other transistors
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dt = &(g_tp.peri_global);
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}
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return nwidth * dt->I_off_n;
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}
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int factorial(int n, int m)
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{
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int fa = m, i;
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for (i=m+1; i<=n; i++)
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fa *=i;
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return fa;
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}
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int combination(int n, int m)
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{
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int ret;
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ret = factorial(n, m+1) / factorial(n - m);
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return ret;
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}
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double simplified_pmos_leakage(
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double pwidth,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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TechnologyParameter::DeviceType * dt;
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if ((!_is_dram)&&(_is_cell))
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{ //SRAM cell access transistor
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dt = &(g_tp.sram_cell);
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}
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else if ((_is_dram)&&(_is_wl_tr))
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{ //DRAM wordline transistor
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dt = &(g_tp.dram_wl);
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}
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else
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{ //DRAM or SRAM all other transistors
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dt = &(g_tp.peri_global);
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}
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return pwidth * dt->I_off_p;
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}
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double cmos_Ig_n(
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double nWidth,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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TechnologyParameter::DeviceType * dt;
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if ((!_is_dram)&&(_is_cell))
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{ //SRAM cell access transistor
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dt = &(g_tp.sram_cell);
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}
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else if ((_is_dram)&&(_is_wl_tr))
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{ //DRAM wordline transistor
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dt = &(g_tp.dram_wl);
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}
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else
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{ //DRAM or SRAM all other transistors
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dt = &(g_tp.peri_global);
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}
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return nWidth*dt->I_g_on_n;
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}
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double cmos_Ig_p(
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double pWidth,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr)
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{
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TechnologyParameter::DeviceType * dt;
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if ((!_is_dram)&&(_is_cell))
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{ //SRAM cell access transistor
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dt = &(g_tp.sram_cell);
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}
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else if ((_is_dram)&&(_is_wl_tr))
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{ //DRAM wordline transistor
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dt = &(g_tp.dram_wl);
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}
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else
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{ //DRAM or SRAM all other transistors
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dt = &(g_tp.peri_global);
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}
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return pWidth*dt->I_g_on_p;
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}
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double cmos_Isub_leakage(
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double nWidth,
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double pWidth,
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int fanin,
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enum Gate_type g_type,
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bool _is_dram,
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bool _is_cell,
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bool _is_wl_tr,
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enum Half_net_topology topo)
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{
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assert (fanin>=1);
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double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, _is_wl_tr);
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double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, _is_wl_tr);
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double Isub=0;
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int num_states;
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int num_off_tx;
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num_states = int(pow(2.0, fanin));
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switch (g_type)
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{
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case nmos:
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if (fanin==1)
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{
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Isub = nmos_leak/num_states;
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}
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else
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{
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if (topo==parallel)
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{
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Isub=nmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
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}
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else
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{
|
|
for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
|
|
{
|
|
//Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
|
|
Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
|
|
}
|
|
Isub /=num_states;
|
|
}
|
|
|
|
}
|
|
break;
|
|
case pmos:
|
|
if (fanin==1)
|
|
{
|
|
Isub = pmos_leak/num_states;
|
|
}
|
|
else
|
|
{
|
|
if (topo==parallel)
|
|
{
|
|
Isub=pmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
|
|
}
|
|
else
|
|
{
|
|
for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
|
|
{
|
|
//Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
|
|
Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
|
|
}
|
|
Isub /=num_states;
|
|
}
|
|
|
|
}
|
|
break;
|
|
case inv:
|
|
Isub = (nmos_leak + pmos_leak)/2;
|
|
break;
|
|
case nand:
|
|
Isub += fanin*pmos_leak;//the pullup network
|
|
for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pulldown network
|
|
{
|
|
//Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
|
|
Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
|
|
}
|
|
Isub /=num_states;
|
|
break;
|
|
case nor:
|
|
for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pullup network
|
|
{
|
|
//Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
|
|
Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
|
|
}
|
|
Isub += fanin*nmos_leak;//the pulldown network
|
|
Isub /=num_states;
|
|
break;
|
|
case tri:
|
|
Isub += (nmos_leak + pmos_leak)/2;//enabled
|
|
Isub += nmos_leak*UNI_LEAK_STACK_FACTOR; //disabled upper bound of leakage power
|
|
Isub /=2;
|
|
break;
|
|
case tg:
|
|
Isub = (nmos_leak + pmos_leak)/2;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
break;
|
|
}
|
|
|
|
return Isub;
|
|
}
|
|
|
|
|
|
double cmos_Ig_leakage(
|
|
double nWidth,
|
|
double pWidth,
|
|
int fanin,
|
|
enum Gate_type g_type,
|
|
bool _is_dram,
|
|
bool _is_cell,
|
|
bool _is_wl_tr,
|
|
enum Half_net_topology topo)
|
|
{
|
|
assert (fanin>=1);
|
|
double nmos_leak = cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr);
|
|
double pmos_leak = cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr);
|
|
double Ig_on=0;
|
|
int num_states;
|
|
int num_on_tx;
|
|
|
|
num_states = int(pow(2.0, fanin));
|
|
|
|
switch (g_type)
|
|
{
|
|
case nmos:
|
|
if (fanin==1)
|
|
{
|
|
Ig_on = nmos_leak/num_states;
|
|
}
|
|
else
|
|
{
|
|
if (topo==parallel)
|
|
{
|
|
for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
|
|
{
|
|
Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
|
|
//num_on_tx is the number of on tx
|
|
for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
|
|
{
|
|
Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
|
|
}
|
|
Ig_on /=num_states;
|
|
}
|
|
}
|
|
break;
|
|
case pmos:
|
|
if (fanin==1)
|
|
{
|
|
Ig_on = pmos_leak/num_states;
|
|
}
|
|
else
|
|
{
|
|
if (topo==parallel)
|
|
{
|
|
for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
|
|
{
|
|
Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Ig_on += pmos_leak * fanin;//pull down network when all TXs are on.
|
|
//num_on_tx is the number of on tx
|
|
for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
|
|
{
|
|
Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
|
|
}
|
|
Ig_on /=num_states;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case inv:
|
|
Ig_on = (nmos_leak + pmos_leak)/2;
|
|
break;
|
|
case nand:
|
|
//pull up network
|
|
for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
|
|
{
|
|
Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
|
|
}
|
|
|
|
//pull down network
|
|
Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
|
|
//num_on_tx is the number of on tx
|
|
for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
|
|
{
|
|
Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
|
|
}
|
|
Ig_on /=num_states;
|
|
break;
|
|
case nor:
|
|
// num_on_tx is the number of on tx in pull up network
|
|
Ig_on += pmos_leak * fanin;//pull up network when all TXs are on.
|
|
for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)
|
|
{
|
|
Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;
|
|
|
|
}
|
|
//pull down network
|
|
for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
|
|
{
|
|
Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
|
|
}
|
|
Ig_on /=num_states;
|
|
break;
|
|
case tri:
|
|
Ig_on += (2*nmos_leak + 2*pmos_leak)/2;//enabled
|
|
Ig_on += (nmos_leak + pmos_leak)/2; //disabled upper bound of leakage power
|
|
Ig_on /=2;
|
|
break;
|
|
case tg:
|
|
Ig_on = (nmos_leak + pmos_leak)/2;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
break;
|
|
}
|
|
|
|
return Ig_on;
|
|
}
|
|
|
|
double shortcircuit_simple(
|
|
double vt,
|
|
double velocity_index,
|
|
double c_in,
|
|
double c_out,
|
|
double w_nmos,
|
|
double w_pmos,
|
|
double i_on_n,
|
|
double i_on_p,
|
|
double i_on_n_in,
|
|
double i_on_p_in,
|
|
double vdd)
|
|
{
|
|
|
|
double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
|
|
double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
|
|
|
|
fo_n = i_on_n/i_on_n_in;
|
|
fo_p = i_on_p/i_on_p_in;
|
|
fanout = c_out/c_in;
|
|
beta_ratio = i_on_p/i_on_n;
|
|
vt_to_vdd_ratio = vt/vdd;
|
|
|
|
//p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
|
|
p_short_circuit_discharge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
|
|
p_short_circuit_charge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_n*fo_n/fanout*beta_ratio;
|
|
// double t1, t2, t3, t4, t5;
|
|
// t1=pow(((vdd-vt)-vt_to_vdd_ratio),3);
|
|
// t2=pow(velocity_index,2.0);
|
|
// t3=pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio);
|
|
// t4=t1/t2/t3;
|
|
// cout <<t1<<"t1\n"<<t2<<"t2\n"<<t3<<"t3\n"<<t4<<"t4\n"<<fanout<<endl;
|
|
|
|
p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
|
|
p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
|
|
|
|
// t1=pow(((vdd-vt)-vt_to_vdd_ratio),1.5);
|
|
// t2=pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
|
|
// t3=t1/t2;
|
|
// cout <<t1<<"t1\n"<<t2<<"t2\n"<<t3<<"t3\n"<<t4<<"t4\n"<<fanout<<endl;
|
|
// p_short_circuit_discharge = 1.0/(1.0/p_short_circuit_discharge_low + 1.0/p_short_circuit_discharge_high);
|
|
// p_short_circuit_charge = 1/(1/p_short_circuit_charge_low + 1/p_short_circuit_charge_high); //harmmoic mean cannot be applied simple formulas.
|
|
|
|
p_short_circuit_discharge = p_short_circuit_discharge_low;
|
|
p_short_circuit_charge = p_short_circuit_charge_low;
|
|
p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge)/2;
|
|
|
|
return (p_short_circuit);
|
|
}
|
|
|
|
double shortcircuit(
|
|
double vt,
|
|
double velocity_index,
|
|
double c_in,
|
|
double c_out,
|
|
double w_nmos,
|
|
double w_pmos,
|
|
double i_on_n,
|
|
double i_on_p,
|
|
double i_on_n_in,
|
|
double i_on_p_in,
|
|
double vdd)
|
|
{
|
|
|
|
double p_short_circuit=0, p_short_circuit_discharge;//, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
|
|
double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
|
|
double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
|
|
|
|
fo_n = i_on_n/i_on_n_in;
|
|
fo_p = i_on_p/i_on_p_in;
|
|
fanout = 1;
|
|
beta_ratio = i_on_p/i_on_n;
|
|
vt_to_vdd_ratio = vt/vdd;
|
|
e = 2.71828;
|
|
f_alpha = 1/(velocity_index+2) -velocity_index/(2*(velocity_index+3)) +velocity_index/(velocity_index+4)*(velocity_index/2-1);
|
|
k_v = 0.9/0.8+(vdd-vt)/0.8*log(10*(vdd-vt)/e);
|
|
g_v_alpha = (velocity_index + 1)*pow((1-velocity_index),velocity_index)*pow((1-velocity_index),velocity_index/2)/f_alpha/pow((1-velocity_index-velocity_index),(velocity_index/2+velocity_index+2));
|
|
h_v_alpha = pow(2, velocity_index)*(velocity_index+1)*pow((1-velocity_index),velocity_index)/pow((1-velocity_index-velocity_index),(velocity_index+1));
|
|
|
|
//p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
|
|
// p_short_circuit_discharge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
|
|
// p_short_circuit_charge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_n*fo_n/fanout*beta_ratio;
|
|
// double t1, t2, t3, t4, t5;
|
|
// t1=pow(((vdd-vt)-vt_to_vdd_ratio),3);
|
|
// t2=pow(velocity_index,2.0);
|
|
// t3=pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio);
|
|
// t4=t1/t2/t3;
|
|
//
|
|
// cout <<t1<<"t1\n"<<t2<<"t2\n"<<t3<<"t3\n"<<t4<<"t4\n"<<fanout<<endl;
|
|
//
|
|
//
|
|
// p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
|
|
// p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
|
|
//
|
|
// p_short_circuit_discharge = 1.0/(1.0/p_short_circuit_discharge_low + 1.0/p_short_circuit_discharge_high);
|
|
// p_short_circuit_charge = 1/(1/p_short_circuit_charge_low + 1/p_short_circuit_charge_high);
|
|
//
|
|
// p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge)/2;
|
|
//
|
|
// p_short_circuit = p_short_circuit_discharge;
|
|
|
|
p_short_circuit_discharge = k_v*vdd*vdd*c_in*fo_p*fo_p/((vdd-vt)*g_v_alpha*fanout*beta_ratio/2/k_v + h_v_alpha*fo_p);
|
|
return (p_short_circuit);
|
|
}
|