612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
125 lines
3 KiB
ArmAsm
125 lines
3 KiB
ArmAsm
/*
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* boot.S - simple register setup code for stand-alone Linux booting
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*
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* Copyright (C) 2012 ARM Limited. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE.txt file.
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*/
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.text
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.globl _start
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_start:
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/*
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* EL3 initialisation
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*/
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mrs x0, CurrentEL
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cmp x0, #0xc // EL3?
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b.ne start_ns // skip EL3 initialisation
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mov x0, #0x30 // RES1
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orr x0, x0, #(1 << 0) // Non-secure EL1
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orr x0, x0, #(1 << 8) // HVC enable
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orr x0, x0, #(1 << 10) // 64-bit EL2
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msr scr_el3, x0
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msr cptr_el3, xzr // Disable copro. traps to EL3
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ldr x0, =CNTFRQ
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msr cntfrq_el0, x0
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/*
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* Check for the primary CPU to avoid a race on the distributor
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* registers.
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*/
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mrs x0, mpidr_el1
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tst x0, #15
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b.ne 1f // secondary CPU
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ldr x1, =GIC_DIST_BASE // GICD_CTLR
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
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mov w0, #~0 // Grp1 interrupts
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str w0, [x1], #4
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b.ne 2f // Only local interrupts for secondary CPUs
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str w0, [x1], #4
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str w0, [x1], #4
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2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
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ldr w0, [x1]
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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mov w0, #1 << 7 // allow NS access to GICC_PMR
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str w0, [x1, #4] // GICC_PMR
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msr sctlr_el2, xzr
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/*
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* Prepare the switch to the EL2_SP1 mode from EL3
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*/
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ldr x0, =start_ns // Return after mode switch
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mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
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msr elr_el3, x0
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msr spsr_el3, x1
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eret
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start_ns:
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/*
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* Kernel parameters
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*/
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mov x0, xzr
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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mrs x4, mpidr_el1
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tst x4, #15
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b.eq 2f
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/*
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* Secondary CPUs
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*/
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1: wfe
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ldr x4, =PHYS_OFFSET + 0xfff8
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ldr x4, [x4]
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cbz x4, 1b
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br x4 // branch to the given address
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2:
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/*
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* UART initialisation (38400 8N1)
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*/
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ldr x4, =UART_BASE // UART base
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mov w5, #0x10 // ibrd
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str w5, [x4, #0x24]
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mov w5, #0xc300
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orr w5, w5, #0x0001 // cr
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str w5, [x4, #0x30]
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/*
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* CLCD output site MB
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*/
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ldr x4, =SYSREGS_BASE
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ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
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str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
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str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
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// set up the arch timer frequency
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//ldr x0, =CNTFRQ
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//msr cntfrq_el0, x0
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/*
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* Primary CPU
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*/
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ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
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ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
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br x6
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.ltorg
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.org 0x200
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