8bc925e36d
This patch aligns how the memory-system slaves, i.e. the various memory controllers and the bridge, identify and deal with sinking of inhibited packets that are only useful within the coherent part of the memory system. In the future we could shift the onus to the crossbar, and add a parameter "is_point_of_coherence" that would allow it to sink the aforementioned packets.
280 lines
8 KiB
C++
280 lines
8 KiB
C++
/*
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* Copyright (c) 2010-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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* Andreas Hansson
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*/
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#include "base/random.hh"
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#include "mem/simple_mem.hh"
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#include "debug/Drain.hh"
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using namespace std;
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SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
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AbstractMemory(p),
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port(name() + ".port", *this), latency(p->latency),
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latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
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retryReq(false), retryResp(false),
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releaseEvent(this), dequeueEvent(this)
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{
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}
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void
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SimpleMemory::init()
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{
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AbstractMemory::init();
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// allow unconnected memories as this is used in several ruby
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// systems at the moment
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if (port.isConnected()) {
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port.sendRangeChange();
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}
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}
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Tick
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SimpleMemory::recvAtomic(PacketPtr pkt)
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{
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access(pkt);
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return pkt->memInhibitAsserted() ? 0 : getLatency();
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}
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void
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SimpleMemory::recvFunctional(PacketPtr pkt)
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{
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pkt->pushLabel(name());
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functionalAccess(pkt);
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bool done = false;
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auto p = packetQueue.begin();
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// potentially update the packets in our packet queue as well
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while (!done && p != packetQueue.end()) {
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done = pkt->checkFunctional(p->pkt);
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++p;
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}
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pkt->popLabel();
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}
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bool
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SimpleMemory::recvTimingReq(PacketPtr pkt)
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{
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// sink inhibited packets without further action
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if (pkt->memInhibitAsserted()) {
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pendingDelete.reset(pkt);
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return true;
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}
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// we should not get a new request after committing to retry the
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// current one, but unfortunately the CPU violates this rule, so
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// simply ignore it for now
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if (retryReq)
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return false;
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// if we are busy with a read or write, remember that we have to
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// retry
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if (isBusy) {
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retryReq = true;
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return false;
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}
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// @todo someone should pay for this
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pkt->headerDelay = pkt->payloadDelay = 0;
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// update the release time according to the bandwidth limit, and
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// do so with respect to the time it takes to finish this request
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// rather than long term as it is the short term data rate that is
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// limited for any real memory
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// only look at reads and writes when determining if we are busy,
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// and for how long, as it is not clear what to regulate for the
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// other types of commands
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if (pkt->isRead() || pkt->isWrite()) {
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// calculate an appropriate tick to release to not exceed
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// the bandwidth limit
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Tick duration = pkt->getSize() * bandwidth;
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// only consider ourselves busy if there is any need to wait
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// to avoid extra events being scheduled for (infinitely) fast
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// memories
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if (duration != 0) {
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schedule(releaseEvent, curTick() + duration);
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isBusy = true;
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}
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}
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// go ahead and deal with the packet and put the response in the
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// queue if there is one
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bool needsResponse = pkt->needsResponse();
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recvAtomic(pkt);
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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// recvAtomic() should already have turned packet into
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// atomic response
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assert(pkt->isResponse());
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// to keep things simple (and in order), we put the packet at
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// the end even if the latency suggests it should be sent
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// before the packet(s) before it
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packetQueue.emplace_back(pkt, curTick() + getLatency());
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if (!retryResp && !dequeueEvent.scheduled())
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schedule(dequeueEvent, packetQueue.back().tick);
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} else {
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pendingDelete.reset(pkt);
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}
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return true;
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}
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void
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SimpleMemory::release()
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{
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assert(isBusy);
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isBusy = false;
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if (retryReq) {
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retryReq = false;
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port.sendRetryReq();
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}
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}
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void
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SimpleMemory::dequeue()
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{
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assert(!packetQueue.empty());
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DeferredPacket deferred_pkt = packetQueue.front();
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retryResp = !port.sendTimingResp(deferred_pkt.pkt);
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if (!retryResp) {
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packetQueue.pop_front();
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// if the queue is not empty, schedule the next dequeue event,
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// otherwise signal that we are drained if we were asked to do so
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if (!packetQueue.empty()) {
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// if there were packets that got in-between then we
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// already have an event scheduled, so use re-schedule
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reschedule(dequeueEvent,
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std::max(packetQueue.front().tick, curTick()), true);
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} else if (drainState() == DrainState::Draining) {
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DPRINTF(Drain, "Draining of SimpleMemory complete\n");
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signalDrainDone();
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}
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}
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}
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Tick
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SimpleMemory::getLatency() const
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{
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return latency +
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(latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
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}
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void
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SimpleMemory::recvRespRetry()
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{
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assert(retryResp);
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dequeue();
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}
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BaseSlavePort &
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SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name != "port") {
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return MemObject::getSlavePort(if_name, idx);
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} else {
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return port;
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}
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}
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DrainState
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SimpleMemory::drain()
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{
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if (!packetQueue.empty()) {
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DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
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return DrainState::Draining;
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} else {
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return DrainState::Drained;
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}
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}
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SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
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SimpleMemory& _memory)
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: SlavePort(_name, &_memory), memory(_memory)
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{ }
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AddrRangeList
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SimpleMemory::MemoryPort::getAddrRanges() const
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{
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AddrRangeList ranges;
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ranges.push_back(memory.getAddrRange());
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return ranges;
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}
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Tick
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SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
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{
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return memory.recvAtomic(pkt);
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}
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void
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SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
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{
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memory.recvFunctional(pkt);
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}
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bool
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SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
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{
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return memory.recvTimingReq(pkt);
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}
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void
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SimpleMemory::MemoryPort::recvRespRetry()
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{
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memory.recvRespRetry();
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}
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SimpleMemory*
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SimpleMemoryParams::create()
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{
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return new SimpleMemory(this);
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}
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