695 lines
23 KiB
C++
695 lines
23 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/str.hh"
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#include "cpu/rubytest/RubyTester.hh"
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#include "mem/protocol/CacheMsg.hh"
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#include "mem/protocol/Protocol.hh"
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#include "mem/protocol/Protocol.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/common/SubBlock.hh"
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#include "mem/ruby/libruby.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/recorder/Tracer.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/ruby/system/System.hh"
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#include "mem/packet.hh"
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#include "params/RubySequencer.hh"
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using namespace std;
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Sequencer *
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RubySequencerParams::create()
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{
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return new Sequencer(this);
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}
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Sequencer::Sequencer(const Params *p)
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: RubyPort(p), deadlockCheckEvent(this)
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{
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m_store_waiting_on_load_cycles = 0;
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m_store_waiting_on_store_cycles = 0;
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m_load_waiting_on_store_cycles = 0;
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m_load_waiting_on_load_cycles = 0;
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m_outstanding_count = 0;
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m_max_outstanding_requests = 0;
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m_deadlock_threshold = 0;
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m_instCache_ptr = NULL;
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m_dataCache_ptr = NULL;
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m_instCache_ptr = p->icache;
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m_dataCache_ptr = p->dcache;
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m_max_outstanding_requests = p->max_outstanding_requests;
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m_deadlock_threshold = p->deadlock_threshold;
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m_usingRubyTester = p->using_ruby_tester;
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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assert(m_instCache_ptr != NULL);
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assert(m_dataCache_ptr != NULL);
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}
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Sequencer::~Sequencer()
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{
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}
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void
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Sequencer::wakeup()
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{
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// Check for deadlock of any of the requests
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Time current_time = g_eventQueue_ptr->getTime();
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// Check across all outstanding requests
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int total_outstanding = 0;
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RequestTable::iterator read = m_readRequestTable.begin();
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RequestTable::iterator read_end = m_readRequestTable.end();
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for (; read != read_end; ++read) {
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SequencerRequest* request = read->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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WARN_MSG("Possible Deadlock detected");
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WARN_EXPR(m_version);
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WARN_EXPR(request->ruby_request.paddr);
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WARN_EXPR(m_readRequestTable.size());
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WARN_EXPR(current_time);
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WARN_EXPR(request->issue_time);
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WARN_EXPR(current_time - request->issue_time);
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ERROR_MSG("Aborting");
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}
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RequestTable::iterator write = m_writeRequestTable.begin();
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RequestTable::iterator write_end = m_writeRequestTable.end();
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for (; write != write_end; ++write) {
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SequencerRequest* request = write->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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WARN_MSG("Possible Deadlock detected");
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WARN_EXPR(m_version);
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WARN_EXPR(request->ruby_request.paddr);
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WARN_EXPR(current_time);
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WARN_EXPR(request->issue_time);
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WARN_EXPR(current_time - request->issue_time);
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WARN_EXPR(m_writeRequestTable.size());
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ERROR_MSG("Aborting");
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}
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total_outstanding += m_writeRequestTable.size();
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total_outstanding += m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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if (m_outstanding_count > 0) {
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// If there are still outstanding requests, keep checking
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schedule(deadlockCheckEvent,
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m_deadlock_threshold * g_eventQueue_ptr->getClock() +
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curTick);
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}
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}
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void
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Sequencer::printStats(ostream & out) const
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{
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out << "Sequencer: " << m_name << endl
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<< " store_waiting_on_load_cycles: "
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<< m_store_waiting_on_load_cycles << endl
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<< " store_waiting_on_store_cycles: "
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<< m_store_waiting_on_store_cycles << endl
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<< " load_waiting_on_load_cycles: "
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<< m_load_waiting_on_load_cycles << endl
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<< " load_waiting_on_store_cycles: "
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<< m_load_waiting_on_store_cycles << endl;
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}
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void
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Sequencer::printProgress(ostream& out) const
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{
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#if 0
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int total_demand = 0;
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out << "Sequencer Stats Version " << m_version << endl;
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out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
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out << "---------------" << endl;
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out << "outstanding requests" << endl;
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out << "proc " << m_Read
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<< " version Requests = " << m_readRequestTable.size() << endl;
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// print the request table
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RequestTable::iterator read = m_readRequestTable.begin();
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RequestTable::iterator read_end = m_readRequestTable.end();
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for (; read != read_end; ++read) {
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SequencerRequest* request = read->second;
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out << "\tRequest[ " << i << " ] = " << request->type
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<< " Address " << rkeys[i]
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<< " Posted " << request->issue_time
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<< " PF " << PrefetchBit_No << endl;
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total_demand++;
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}
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out << "proc " << m_version
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<< " Write Requests = " << m_writeRequestTable.size << endl;
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// print the request table
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RequestTable::iterator write = m_writeRequestTable.begin();
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RequestTable::iterator write_end = m_writeRequestTable.end();
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for (; write != write_end; ++write) {
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SequencerRequest* request = write->second;
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out << "\tRequest[ " << i << " ] = " << request.getType()
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<< " Address " << wkeys[i]
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<< " Posted " << request.getTime()
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<< " PF " << request.getPrefetch() << endl;
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if (request.getPrefetch() == PrefetchBit_No) {
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total_demand++;
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}
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}
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out << endl;
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out << "Total Number Outstanding: " << m_outstanding_count << endl
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<< "Total Number Demand : " << total_demand << endl
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<< "Total Number Prefetches : " << m_outstanding_count - total_demand
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<< endl << endl << endl;
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#endif
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}
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void
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Sequencer::printConfig(ostream& out) const
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{
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out << "Seqeuncer config: " << m_name << endl
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<< " controller: " << m_controller->getName() << endl
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<< " version: " << m_version << endl
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<< " max_outstanding_requests: " << m_max_outstanding_requests << endl
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<< " deadlock_threshold: " << m_deadlock_threshold << endl;
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}
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// Insert the request on the correct request table. Return true if
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// the entry was already present.
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bool
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Sequencer::insertRequest(SequencerRequest* request)
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{
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int total_outstanding =
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m_writeRequestTable.size() + m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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// See if we should schedule a deadlock check
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if (deadlockCheckEvent.scheduled() == false) {
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schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
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}
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Address line_addr(request->ruby_request.paddr);
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line_addr.makeLineAddress();
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if ((request->ruby_request.type == RubyRequestType_ST) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_RMW_Write) ||
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(request->ruby_request.type == RubyRequestType_Locked_Read) ||
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(request->ruby_request.type == RubyRequestType_Locked_Write)) {
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pair<RequestTable::iterator, bool> r =
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m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
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bool success = r.second;
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RequestTable::iterator i = r.first;
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if (!success) {
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i->second = request;
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// return true;
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// drh5: isn't this an error? do you lose the initial request?
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assert(0);
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}
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i->second = request;
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m_outstanding_count++;
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} else {
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pair<RequestTable::iterator, bool> r =
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m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
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bool success = r.second;
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RequestTable::iterator i = r.first;
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if (!success) {
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i->second = request;
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// return true;
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// drh5: isn't this an error? do you lose the initial request?
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assert(0);
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}
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i->second = request;
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m_outstanding_count++;
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}
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g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
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total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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return false;
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}
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void
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Sequencer::markRemoved()
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{
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m_outstanding_count--;
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assert(m_outstanding_count ==
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m_writeRequestTable.size() + m_readRequestTable.size());
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}
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void
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Sequencer::removeRequest(SequencerRequest* srequest)
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{
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assert(m_outstanding_count ==
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m_writeRequestTable.size() + m_readRequestTable.size());
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const RubyRequest & ruby_request = srequest->ruby_request;
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Address line_addr(ruby_request.paddr);
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line_addr.makeLineAddress();
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if ((ruby_request.type == RubyRequestType_ST) ||
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(ruby_request.type == RubyRequestType_RMW_Read) ||
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(ruby_request.type == RubyRequestType_RMW_Write) ||
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(ruby_request.type == RubyRequestType_Locked_Read) ||
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(ruby_request.type == RubyRequestType_Locked_Write)) {
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m_writeRequestTable.erase(line_addr);
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} else {
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m_readRequestTable.erase(line_addr);
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}
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markRemoved();
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}
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bool
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Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
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{
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//
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// The success flag indicates whether the LLSC operation was successful.
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// LL ops will always succeed, but SC may fail if the cache line is no
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// longer locked.
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//
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bool success = true;
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if (request->ruby_request.type == RubyRequestType_Locked_Write) {
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if (!m_dataCache_ptr->isLocked(address, m_version)) {
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//
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// For failed SC requests, indicate the failure to the cpu by
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// setting the extra data to zero.
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//
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request->ruby_request.pkt->req->setExtraData(0);
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success = false;
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} else {
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//
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// For successful SC requests, indicate the success to the cpu by
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// setting the extra data to one.
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//
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request->ruby_request.pkt->req->setExtraData(1);
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}
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//
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// Independent of success, all SC operations must clear the lock
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//
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m_dataCache_ptr->clearLocked(address);
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} else if (request->ruby_request.type == RubyRequestType_Locked_Read) {
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//
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// Note: To fully follow Alpha LLSC semantics, should the LL clear any
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// previously locked cache lines?
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//
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m_dataCache_ptr->setLocked(address, m_version);
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} else if (m_dataCache_ptr->isLocked(address, m_version)) {
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//
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// Normal writes should clear the locked address
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//
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m_dataCache_ptr->clearLocked(address);
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}
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return success;
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}
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void
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Sequencer::writeCallback(const Address& address, DataBlock& data)
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{
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writeCallback(address, GenericMachineType_NULL, data);
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}
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void
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Sequencer::writeCallback(const Address& address,
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GenericMachineType mach,
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DataBlock& data)
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{
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assert(address == line_address(address));
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assert(m_writeRequestTable.count(line_address(address)));
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RequestTable::iterator i = m_writeRequestTable.find(address);
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assert(i != m_writeRequestTable.end());
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SequencerRequest* request = i->second;
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m_writeRequestTable.erase(i);
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markRemoved();
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assert((request->ruby_request.type == RubyRequestType_ST) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_RMW_Write) ||
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(request->ruby_request.type == RubyRequestType_Locked_Read) ||
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(request->ruby_request.type == RubyRequestType_Locked_Write));
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//
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// For Alpha, properly handle LL, SC, and write requests with respect to
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// locked cache blocks.
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//
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bool success = handleLlsc(address, request);
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if (request->ruby_request.type == RubyRequestType_RMW_Read) {
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m_controller->blockOnQueue(address, m_mandatory_q_ptr);
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} else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
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m_controller->unblock(address);
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}
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hitCallback(request, mach, data, success);
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}
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void
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Sequencer::readCallback(const Address& address, DataBlock& data)
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{
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readCallback(address, GenericMachineType_NULL, data);
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}
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void
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Sequencer::readCallback(const Address& address,
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GenericMachineType mach,
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DataBlock& data)
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{
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assert(address == line_address(address));
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assert(m_readRequestTable.count(line_address(address)));
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RequestTable::iterator i = m_readRequestTable.find(address);
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assert(i != m_readRequestTable.end());
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SequencerRequest* request = i->second;
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m_readRequestTable.erase(i);
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markRemoved();
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assert((request->ruby_request.type == RubyRequestType_LD) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_IFETCH));
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hitCallback(request, mach, data, true);
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}
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void
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Sequencer::hitCallback(SequencerRequest* srequest,
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GenericMachineType mach,
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DataBlock& data,
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bool success)
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{
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const RubyRequest & ruby_request = srequest->ruby_request;
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Address request_address(ruby_request.paddr);
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Address request_line_address(ruby_request.paddr);
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request_line_address.makeLineAddress();
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RubyRequestType type = ruby_request.type;
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Time issued_time = srequest->issue_time;
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// Set this cache entry to the most recently used
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if (type == RubyRequestType_IFETCH) {
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if (m_instCache_ptr->isTagPresent(request_line_address))
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m_instCache_ptr->setMRU(request_line_address);
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} else {
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if (m_dataCache_ptr->isTagPresent(request_line_address))
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m_dataCache_ptr->setMRU(request_line_address);
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}
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assert(g_eventQueue_ptr->getTime() >= issued_time);
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Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
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// Profile the miss latency for all non-zero demand misses
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if (miss_latency != 0) {
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g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
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if (Debug::getProtocolTrace()) {
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if (success) {
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g_system_ptr->getProfiler()->
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profileTransition("Seq", m_version,
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Address(ruby_request.paddr), "", "Done", "",
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csprintf("%d cycles", miss_latency));
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} else {
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g_system_ptr->getProfiler()->
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profileTransition("Seq", m_version,
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Address(ruby_request.paddr), "", "SC_Failed", "",
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csprintf("%d cycles", miss_latency));
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}
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}
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}
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#if 0
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if (request.getPrefetch() == PrefetchBit_Yes) {
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return; // Ignore the prefetch
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}
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#endif
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// update the data
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if (ruby_request.data != NULL) {
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if ((type == RubyRequestType_LD) ||
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(type == RubyRequestType_IFETCH) ||
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(type == RubyRequestType_RMW_Read) ||
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(type == RubyRequestType_Locked_Read)) {
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memcpy(ruby_request.data,
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data.getData(request_address.getOffset(), ruby_request.len),
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ruby_request.len);
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} else {
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data.setData(ruby_request.data, request_address.getOffset(),
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ruby_request.len);
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}
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} else {
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DPRINTF(MemoryAccess,
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"WARNING. Data not transfered from Ruby to M5 for type %s\n",
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RubyRequestType_to_string(type));
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}
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// If using the RubyTester, update the RubyTester sender state's
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// subBlock with the recieved data. The tester will later access
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// this state.
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// Note: RubyPort will access it's sender state before the
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// RubyTester.
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if (m_usingRubyTester) {
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RubyPort::SenderState *requestSenderState =
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safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
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RubyTester::SenderState* testerSenderState =
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safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
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testerSenderState->subBlock->mergeFrom(data);
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}
|
|
|
|
ruby_hit_callback(ruby_request.pkt);
|
|
delete srequest;
|
|
}
|
|
|
|
// Returns true if the sequencer already has a load or store outstanding
|
|
RequestStatus
|
|
Sequencer::getRequestStatus(const RubyRequest& request)
|
|
{
|
|
bool is_outstanding_store =
|
|
!!m_writeRequestTable.count(line_address(Address(request.paddr)));
|
|
bool is_outstanding_load =
|
|
!!m_readRequestTable.count(line_address(Address(request.paddr)));
|
|
if (is_outstanding_store) {
|
|
if ((request.type == RubyRequestType_LD) ||
|
|
(request.type == RubyRequestType_IFETCH) ||
|
|
(request.type == RubyRequestType_RMW_Read)) {
|
|
m_store_waiting_on_load_cycles++;
|
|
} else {
|
|
m_store_waiting_on_store_cycles++;
|
|
}
|
|
return RequestStatus_Aliased;
|
|
} else if (is_outstanding_load) {
|
|
if ((request.type == RubyRequestType_ST) ||
|
|
(request.type == RubyRequestType_RMW_Write)) {
|
|
m_load_waiting_on_store_cycles++;
|
|
} else {
|
|
m_load_waiting_on_load_cycles++;
|
|
}
|
|
return RequestStatus_Aliased;
|
|
}
|
|
|
|
if (m_outstanding_count >= m_max_outstanding_requests) {
|
|
return RequestStatus_BufferFull;
|
|
}
|
|
|
|
return RequestStatus_Ready;
|
|
}
|
|
|
|
bool
|
|
Sequencer::empty() const
|
|
{
|
|
return m_writeRequestTable.empty() && m_readRequestTable.empty();
|
|
}
|
|
|
|
RequestStatus
|
|
Sequencer::makeRequest(const RubyRequest &request)
|
|
{
|
|
assert(Address(request.paddr).getOffset() + request.len <=
|
|
RubySystem::getBlockSizeBytes());
|
|
RequestStatus status = getRequestStatus(request);
|
|
if (status != RequestStatus_Ready)
|
|
return status;
|
|
|
|
SequencerRequest *srequest =
|
|
new SequencerRequest(request, g_eventQueue_ptr->getTime());
|
|
bool found = insertRequest(srequest);
|
|
if (found) {
|
|
panic("Sequencer::makeRequest should never be called if the "
|
|
"request is already outstanding\n");
|
|
return RequestStatus_NULL;
|
|
}
|
|
|
|
issueRequest(request);
|
|
|
|
// TODO: issue hardware prefetches here
|
|
return RequestStatus_Issued;
|
|
}
|
|
|
|
void
|
|
Sequencer::issueRequest(const RubyRequest& request)
|
|
{
|
|
// TODO: get rid of CacheMsg, CacheRequestType, and
|
|
// AccessModeTYpe, & have SLICC use RubyRequest and subtypes
|
|
// natively
|
|
CacheRequestType ctype;
|
|
switch(request.type) {
|
|
case RubyRequestType_IFETCH:
|
|
ctype = CacheRequestType_IFETCH;
|
|
break;
|
|
case RubyRequestType_LD:
|
|
ctype = CacheRequestType_LD;
|
|
break;
|
|
case RubyRequestType_ST:
|
|
ctype = CacheRequestType_ST;
|
|
break;
|
|
case RubyRequestType_Locked_Read:
|
|
case RubyRequestType_Locked_Write:
|
|
ctype = CacheRequestType_ATOMIC;
|
|
break;
|
|
case RubyRequestType_RMW_Read:
|
|
ctype = CacheRequestType_ATOMIC;
|
|
break;
|
|
case RubyRequestType_RMW_Write:
|
|
ctype = CacheRequestType_ATOMIC;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
}
|
|
|
|
AccessModeType amtype;
|
|
switch(request.access_mode){
|
|
case RubyAccessMode_User:
|
|
amtype = AccessModeType_UserMode;
|
|
break;
|
|
case RubyAccessMode_Supervisor:
|
|
amtype = AccessModeType_SupervisorMode;
|
|
break;
|
|
case RubyAccessMode_Device:
|
|
amtype = AccessModeType_UserMode;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
}
|
|
|
|
Address line_addr(request.paddr);
|
|
line_addr.makeLineAddress();
|
|
CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,
|
|
Address(request.pc), amtype, request.len, PrefetchBit_No,
|
|
request.proc_id);
|
|
|
|
if (Debug::getProtocolTrace()) {
|
|
g_system_ptr->getProfiler()->
|
|
profileTransition("Seq", m_version, Address(request.paddr),
|
|
"", "Begin", "",
|
|
RubyRequestType_to_string(request.type));
|
|
}
|
|
|
|
if (g_system_ptr->getTracer()->traceEnabled()) {
|
|
g_system_ptr->getTracer()->
|
|
traceRequest(this, line_addr, Address(request.pc),
|
|
request.type, g_eventQueue_ptr->getTime());
|
|
}
|
|
|
|
Time latency = 0; // initialzed to an null value
|
|
|
|
if (request.type == RubyRequestType_IFETCH)
|
|
latency = m_instCache_ptr->getLatency();
|
|
else
|
|
latency = m_dataCache_ptr->getLatency();
|
|
|
|
// Send the message to the cache controller
|
|
assert(latency > 0);
|
|
|
|
assert(m_mandatory_q_ptr != NULL);
|
|
m_mandatory_q_ptr->enqueue(msg, latency);
|
|
}
|
|
|
|
#if 0
|
|
bool
|
|
Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
|
|
AccessModeType access_mode,
|
|
int size, DataBlock*& data_ptr)
|
|
{
|
|
CacheMemory *cache =
|
|
(type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
|
|
|
|
return cache->tryCacheAccess(line_address(addr), type, data_ptr);
|
|
}
|
|
#endif
|
|
|
|
template <class KEY, class VALUE>
|
|
std::ostream &
|
|
operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
|
|
{
|
|
typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
|
|
typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
|
|
|
|
out << "[";
|
|
for (; i != end; ++i)
|
|
out << " " << i->first << "=" << i->second;
|
|
out << " ]";
|
|
|
|
return out;
|
|
}
|
|
|
|
void
|
|
Sequencer::print(ostream& out) const
|
|
{
|
|
out << "[Sequencer: " << m_version
|
|
<< ", outstanding requests: " << m_outstanding_count
|
|
<< ", read request table: " << m_readRequestTable
|
|
<< ", write request table: " << m_writeRequestTable
|
|
<< "]";
|
|
}
|
|
|
|
// this can be called from setState whenever coherence permissions are
|
|
// upgraded when invoked, coherence violations will be checked for the
|
|
// given block
|
|
void
|
|
Sequencer::checkCoherence(const Address& addr)
|
|
{
|
|
#ifdef CHECK_COHERENCE
|
|
g_system_ptr->checkGlobalCoherenceInvariant(addr);
|
|
#endif
|
|
}
|