46502851ab
configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops
--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
217 lines
5.2 KiB
ArmAsm
217 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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*/
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#define m5_op 0x01
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#define arm_func 0x00
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#define quiesce_func 0x01
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#define quiescens_func 0x02
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#define quiescecycle_func 0x03
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#define quiescetime_func 0x04
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#define ivlb_func 0x10
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#define ivle_func 0x11
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#define exit_old_func 0x20 // deprectated!
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#define exit_func 0x21
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#define initparam_func 0x30
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#define resetstats_func 0x40
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#define dumpstats_func 0x41
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#define dumprststats_func 0x42
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#define ckpt_func 0x43
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#define readfile_func 0x50
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#define debugbreak_func 0x51
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#define switchcpu_func 0x52
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#define addsymbol_func 0x53
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#define panic_func 0x54
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#define anbegin_func 0x55
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#define anwait_func 0x56
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#define INST(op, ra, rb, func) \
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.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
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#define LEAF(func) \
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.align 3; \
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.globl func; \
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.ent func; \
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func:
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#define RET \
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ret ($26)
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#define END(func) \
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.end func
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#define ARM(reg) INST(m5_op, reg, 0, arm_func)
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#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
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#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
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#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
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#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
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#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func)
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#define IVLE(reg) INST(m5_op, reg, 0, ivle_func)
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#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
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#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
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#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
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#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
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#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
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#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
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#define READFILE INST(m5_op, 0, 0, readfile_func)
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#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
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#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
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#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
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#define PANIC INST(m5_op, 0, 0, panic_func)
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#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
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#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
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.set noreorder
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.align 4
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LEAF(arm)
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ARM(16)
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RET
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END(arm)
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.align 4
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LEAF(quiesce)
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QUIESCE
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RET
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END(quiesce)
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.align 4
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LEAF(quiesceNs)
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QUIESCENS(16)
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RET
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END(quiesceNs)
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.align 4
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LEAF(quiesceCycle)
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QUIESCECYC(16)
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RET
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END(quiesceCycle)
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.align 4
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LEAF(quiesceTime)
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QUIESCETIME
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RET
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END(quiesceTime)
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.align 4
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LEAF(m5_ivlb)
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IVLB(16)
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RET
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END(m5_ivlb)
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.align 4
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LEAF(m5_ivle)
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IVLE(16)
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RET
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END(m5_ivle)
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.align 4
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LEAF(m5_exit)
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M5EXIT(16)
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RET
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END(m5_exit)
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.align 4
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LEAF(m5_initparam)
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INITPARAM(0)
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RET
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END(m5_initparam)
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.align 4
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LEAF(m5_reset_stats)
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RESET_STATS(16, 17)
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RET
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END(m5_reset_stats)
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.align 4
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LEAF(m5_dump_stats)
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DUMP_STATS(16, 17)
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RET
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END(m5_dump_stats)
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.align 4
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LEAF(m5_dumpreset_stats)
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DUMPRST_STATS(16, 17)
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RET
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END(m5_dumpreset_stats)
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.align 4
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LEAF(m5_checkpoint)
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CHECKPOINT(16, 17)
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RET
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END(m5_checkpoint)
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.align 4
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LEAF(m5_readfile)
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READFILE
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RET
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END(m5_readfile)
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.align 4
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LEAF(m5_debugbreak)
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DEBUGBREAK
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RET
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END(m5_debugbreak)
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.align 4
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LEAF(m5_switchcpu)
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SWITCHCPU
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RET
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END(m5_switchcpu)
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.align 4
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LEAF(m5_addsymbol)
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ADDSYMBOL(16, 17)
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RET
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END(m5_addsymbol)
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.align 4
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LEAF(m5_panic)
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PANIC
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RET
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END(m5_panic)
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.align 4
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LEAF(m5_anbegin)
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AN_BEGIN(16)
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RET
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END(m5_anbegin)
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.align 4
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LEAF(m5_anwait)
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AN_WAIT(16,17)
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RET
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END(m5_anwait)
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