1b6355c895
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
355 lines
9.9 KiB
C++
355 lines
9.9 KiB
C++
/*
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* Copyright (c) 2011-2014 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Dave Greene
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* Nathan Binkert
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* Andrew Bardsley
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*/
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/**
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* @file
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*
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* ExecContext bears the exec_context interface for Minor.
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*/
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#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
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#define __CPU_MINOR_EXEC_CONTEXT_HH__
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#include "cpu/exec_context.hh"
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#include "cpu/minor/execute.hh"
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#include "cpu/minor/pipeline.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "debug/MinorExecute.hh"
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namespace Minor
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{
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/* Forward declaration of Execute */
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class Execute;
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/** ExecContext bears the exec_context interface for Minor. This nicely
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* separates that interface from other classes such as Pipeline, MinorCPU
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* and DynMinorInst and makes it easier to see what state is accessed by it.
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*/
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class ExecContext : public ::ExecContext
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{
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public:
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MinorCPU &cpu;
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/** ThreadState object, provides all the architectural state. */
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SimpleThread &thread;
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/** The execute stage so we can peek at its contents. */
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Execute &execute;
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/** Instruction for the benefit of memory operations and for PC */
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MinorDynInstPtr inst;
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ExecContext (
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MinorCPU &cpu_,
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SimpleThread &thread_, Execute &execute_,
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MinorDynInstPtr inst_) :
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cpu(cpu_),
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thread(thread_),
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execute(execute_),
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inst(inst_)
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{
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DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
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pcState(inst->pc);
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setPredicate(true);
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thread.setIntReg(TheISA::ZeroReg, 0);
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#if THE_ISA == ALPHA_ISA
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thread.setFloatReg(TheISA::ZeroReg, 0.0);
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#endif
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}
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Fault
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initiateMemRead(Addr addr, unsigned int size, unsigned int flags)
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{
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execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
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size, addr, flags, NULL);
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return NoFault;
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}
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Fault
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writeMem(uint8_t *data, unsigned int size, Addr addr,
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unsigned int flags, uint64_t *res)
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{
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execute.getLSQ().pushRequest(inst, false /* store */, data,
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size, addr, flags, res);
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return NoFault;
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}
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IntReg
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readIntRegOperand(const StaticInst *si, int idx)
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{
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return thread.readIntReg(si->srcRegIdx(idx));
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}
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TheISA::FloatReg
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readFloatRegOperand(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread.readFloatReg(reg_idx);
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}
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TheISA::FloatRegBits
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readFloatRegOperandBits(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread.readFloatRegBits(reg_idx);
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}
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void
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setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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{
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thread.setIntReg(si->destRegIdx(idx), val);
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}
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void
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setFloatRegOperand(const StaticInst *si, int idx,
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TheISA::FloatReg val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread.setFloatReg(reg_idx, val);
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}
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void
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setFloatRegOperandBits(const StaticInst *si, int idx,
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TheISA::FloatRegBits val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread.setFloatRegBits(reg_idx, val);
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}
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bool
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readPredicate()
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{
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return thread.readPredicate();
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}
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void
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setPredicate(bool val)
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{
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thread.setPredicate(val);
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}
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TheISA::PCState
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pcState() const
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{
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return thread.pcState();
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}
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void
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pcState(const TheISA::PCState &val)
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{
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thread.pcState(val);
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}
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TheISA::MiscReg
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readMiscRegNoEffect(int misc_reg) const
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{
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return thread.readMiscRegNoEffect(misc_reg);
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}
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TheISA::MiscReg
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readMiscReg(int misc_reg)
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{
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return thread.readMiscReg(misc_reg);
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}
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void
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setMiscReg(int misc_reg, const TheISA::MiscReg &val)
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{
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thread.setMiscReg(misc_reg, val);
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}
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TheISA::MiscReg
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readMiscRegOperand(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
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return thread.readMiscReg(reg_idx);
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}
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void
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setMiscRegOperand(const StaticInst *si, int idx,
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const TheISA::MiscReg &val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
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return thread.setMiscReg(reg_idx, val);
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}
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Fault
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hwrei()
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{
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#if THE_ISA == ALPHA_ISA
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return thread.hwrei();
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#else
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return NoFault;
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#endif
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}
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bool
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simPalCheck(int palFunc)
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{
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#if THE_ISA == ALPHA_ISA
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return thread.simPalCheck(palFunc);
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#else
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return false;
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#endif
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}
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void
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syscall(int64_t callnum)
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{
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if (FullSystem)
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panic("Syscall emulation isn't available in FS mode.\n");
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thread.syscall(callnum);
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}
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ThreadContext *tcBase() { return thread.getTC(); }
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/* @todo, should make stCondFailures persistent somewhere */
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unsigned int readStCondFailures() const { return 0; }
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void setStCondFailures(unsigned int st_cond_failures) {}
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ContextID contextId() { return thread.contextId(); }
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/* ISA-specific (or at least currently ISA singleton) functions */
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/* X86: TLB twiddling */
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void
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demapPage(Addr vaddr, uint64_t asn)
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{
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thread.getITBPtr()->demapPage(vaddr, asn);
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thread.getDTBPtr()->demapPage(vaddr, asn);
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}
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TheISA::CCReg
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readCCRegOperand(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
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return thread.readCCReg(reg_idx);
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}
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void
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setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
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thread.setCCReg(reg_idx, val);
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}
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void
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demapInstPage(Addr vaddr, uint64_t asn)
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{
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thread.getITBPtr()->demapPage(vaddr, asn);
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}
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void
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demapDataPage(Addr vaddr, uint64_t asn)
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{
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thread.getDTBPtr()->demapPage(vaddr, asn);
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}
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/* ALPHA/POWER: Effective address storage */
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void setEA(Addr ea)
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{
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inst->ea = ea;
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}
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BaseCPU *getCpuPtr() { return &cpu; }
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/* POWER: Effective address storage */
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Addr getEA() const
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{
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return inst->ea;
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}
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/* MIPS: other thread register reading/writing */
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uint64_t
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readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
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{
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SimpleThread *other_thread = (tid == InvalidThreadID
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? &thread : cpu.threads[tid]);
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if (idx < TheISA::FP_Reg_Base) { /* Integer */
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return other_thread->readIntReg(idx);
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} else if (idx < TheISA::Misc_Reg_Base) { /* Float */
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return other_thread->readFloatRegBits(idx
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- TheISA::FP_Reg_Base);
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} else { /* Misc */
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return other_thread->readMiscReg(idx
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- TheISA::Misc_Reg_Base);
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}
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}
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void
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setRegOtherThread(int idx, const TheISA::MiscReg &val,
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ThreadID tid = InvalidThreadID)
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{
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SimpleThread *other_thread = (tid == InvalidThreadID
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? &thread : cpu.threads[tid]);
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if (idx < TheISA::FP_Reg_Base) { /* Integer */
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return other_thread->setIntReg(idx, val);
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} else if (idx < TheISA::Misc_Reg_Base) { /* Float */
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return other_thread->setFloatRegBits(idx
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- TheISA::FP_Reg_Base, val);
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} else { /* Misc */
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return other_thread->setMiscReg(idx
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- TheISA::Misc_Reg_Base, val);
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}
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}
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public:
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// monitor/mwait funtions
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void armMonitor(Addr address) { getCpuPtr()->armMonitor(0, address); }
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bool mwait(PacketPtr pkt) { return getCpuPtr()->mwait(0, pkt); }
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void mwaitAtomic(ThreadContext *tc)
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{ return getCpuPtr()->mwaitAtomic(0, tc, thread.dtb); }
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AddressMonitor *getAddrMonitor()
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{ return getCpuPtr()->getCpuAddrMonitor(0); }
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};
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}
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#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
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