88ab4bb257
This is a hack so that the IO APIC can figure out information about the local APICs. The local APICs still have no way to find out about each other. Ideally, when the local APICs update state that's relevant to somebody else, they'd send an update to everyone. Without being able to do a broadcast, that would still require knowing who else there is to notify. Other broadcasts are implemented using assumptions that may not always be true.
315 lines
8.4 KiB
C++
315 lines
8.4 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_INTERRUPTS_HH__
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#define __ARCH_X86_INTERRUPTS_HH__
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#include "arch/x86/apicregs.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/intmessage.hh"
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#include "base/bitfield.hh"
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#include "cpu/thread_context.hh"
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#include "dev/io_device.hh"
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#include "dev/x86/intdev.hh"
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#include "params/X86LocalApic.hh"
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#include "sim/eventq.hh"
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class ThreadContext;
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class BaseCPU;
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namespace X86ISA {
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class Interrupts : public BasicPioDevice, IntDev
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{
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protected:
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// Storage for the APIC registers
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uint32_t regs[NUM_APIC_REGS];
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BitUnion32(LVTEntry)
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Bitfield<7, 0> vector;
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Bitfield<10, 8> deliveryMode;
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Bitfield<12> status;
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Bitfield<13> polarity;
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Bitfield<14> remoteIRR;
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Bitfield<15> trigger;
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Bitfield<16> masked;
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Bitfield<17> periodic;
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EndBitUnion(LVTEntry)
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/*
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* Timing related stuff.
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*/
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Tick latency;
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Tick clock;
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class ApicTimerEvent : public Event
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{
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private:
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Interrupts *localApic;
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public:
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ApicTimerEvent(Interrupts *_localApic) :
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Event(), localApic(_localApic)
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{}
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void process()
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{
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assert(localApic);
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if (localApic->triggerTimerInterrupt()) {
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localApic->setReg(APIC_INITIAL_COUNT,
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localApic->readReg(APIC_INITIAL_COUNT));
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}
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}
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};
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ApicTimerEvent apicTimerEvent;
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/*
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* A set of variables to keep track of interrupts that don't go through
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* the IRR.
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*/
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bool pendingSmi;
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uint8_t smiVector;
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bool pendingNmi;
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uint8_t nmiVector;
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bool pendingExtInt;
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uint8_t extIntVector;
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bool pendingInit;
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uint8_t initVector;
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bool pendingStartup;
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uint8_t startupVector;
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bool startedUp;
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// This is a quick check whether any of the above (except ExtInt) are set.
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bool pendingUnmaskableInt;
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// A count of how many IPIs are in flight.
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int pendingIPIs;
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/*
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* IRR and ISR maintenance.
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*/
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uint8_t IRRV;
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uint8_t ISRV;
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int
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findRegArrayMSB(ApicRegIndex base)
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{
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int offset = 7;
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do {
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if (regs[base + offset] != 0) {
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return offset * 32 + findMsbSet(regs[base + offset]);
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}
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} while (offset--);
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return 0;
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}
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void
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updateIRRV()
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{
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IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
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}
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void
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updateISRV()
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{
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ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
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}
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void
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setRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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regs[base + (vector / 32)] |= (1 << (vector % 32));
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}
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void
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clearRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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regs[base + (vector / 32)] &= ~(1 << (vector % 32));
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}
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bool
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getRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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return bits(regs[base + (vector / 32)], vector % 5);
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}
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void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
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BaseCPU *cpu;
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int initialApicId;
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public:
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/*
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* Params stuff.
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*/
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typedef X86LocalApicParams Params;
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void setCPU(BaseCPU * newCPU);
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void
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setClock(Tick newClock)
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{
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clock = newClock;
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}
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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/*
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* Initialize this object by registering it with the IO APIC.
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*/
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void init();
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/*
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* Functions to interact with the interrupt port from IntDev.
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*/
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Tick read(PacketPtr pkt);
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Tick write(PacketPtr pkt);
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Tick recvMessage(PacketPtr pkt);
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Tick recvResponse(PacketPtr pkt);
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bool
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triggerTimerInterrupt()
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{
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LVTEntry entry = regs[APIC_LVT_TIMER];
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if (!entry.masked)
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requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
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return entry.periodic;
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}
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void addressRanges(AddrRangeList &range_list);
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void getIntAddrRange(AddrRangeList &range_list);
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Port *getPort(const std::string &if_name, int idx = -1)
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{
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if (if_name == "int_port")
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return intPort;
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return BasicPioDevice::getPort(if_name, idx);
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}
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/*
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* Functions to access and manipulate the APIC's registers.
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*/
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uint32_t readReg(ApicRegIndex miscReg);
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void setReg(ApicRegIndex reg, uint32_t val);
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void
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setRegNoEffect(ApicRegIndex reg, uint32_t val)
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{
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regs[reg] = val;
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}
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/*
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* Constructor.
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*/
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Interrupts(Params * p);
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/*
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* Functions for retrieving interrupts for the CPU to handle.
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*/
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bool checkInterrupts(ThreadContext *tc) const;
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Fault getInterrupt(ThreadContext *tc);
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void updateIntrInfo(ThreadContext *tc);
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/*
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* Serialization.
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*/
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void
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serialize(std::ostream &os)
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{
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panic("Interrupts::serialize unimplemented!\n");
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}
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void
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unserialize(Checkpoint *cp, const std::string §ion)
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{
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panic("Interrupts::unserialize unimplemented!\n");
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}
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/*
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* Old functions needed for compatability but which will be phased out
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* eventually.
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*/
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void
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post(int int_num, int index)
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{
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panic("Interrupts::post unimplemented!\n");
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}
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void
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clear(int int_num, int index)
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{
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panic("Interrupts::clear unimplemented!\n");
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}
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void
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clearAll()
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{
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panic("Interrupts::clearAll unimplemented!\n");
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}
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};
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} // namespace X86ISA
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#endif // __ARCH_X86_INTERRUPTS_HH__
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