835 lines
22 KiB
C++
835 lines
22 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cmath>
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#include <cstdio>
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#include <cstdlib>
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/trace.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/full_cpu/smt.hh"
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#include "cpu/simple_cpu/simple_cpu.hh"
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#include "cpu/static_inst.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "sim/annotation.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_stats.hh"
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#ifdef FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "dev/alpha_access.h"
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#include "dev/pciareg.h"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/system.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "eio/eio.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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void
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SimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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SimpleCPU::TickEvent::description()
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{
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return "SimpleCPU tick event";
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}
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue),
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cpu(_cpu)
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{
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}
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void SimpleCPU::CacheCompletionEvent::process()
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{
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cpu->processCacheCompletion();
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}
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const char *
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SimpleCPU::CacheCompletionEvent::description()
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{
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return "SimpleCPU cache completion event";
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}
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#ifdef FULL_SYSTEM
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SimpleCPU::SimpleCPU(const string &_name,
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System *_system,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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AlphaItb *itb, AlphaDtb *dtb,
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FunctionalMemory *mem,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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Tick freq)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads,
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max_loads_any_thread, max_loads_all_threads,
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_system, freq),
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#else
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SimpleCPU::SimpleCPU(const string &_name, Process *_process,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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MemInterface *icache_interface,
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MemInterface *dcache_interface)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads,
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max_loads_any_thread, max_loads_all_threads),
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#endif
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tickEvent(this), xc(NULL), cacheCompletionEvent(this)
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{
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_status = Idle;
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, system, itb, dtb, mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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#else
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xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
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#endif // !FULL_SYSTEM
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icacheInterface = icache_interface;
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dcacheInterface = dcache_interface;
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memReq = new MemReq();
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memReq->xc = xc;
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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execContexts.push_back(xc);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void
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SimpleCPU::switchOut()
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{
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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void
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SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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oldCPU->switchOut();
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}
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void
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SimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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}
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void
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SimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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void
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SimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::regStats()
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{
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using namespace Statistics;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
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simInsts += numInsts;
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}
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void
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SimpleCPU::resetStats()
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{
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startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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SimpleCPU::serialize(ostream &os)
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{
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SERIALIZE_ENUM(_status);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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xc->serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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cacheCompletionEvent.serialize(os);
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}
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void
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SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_ENUM(_status);
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UNSERIALIZE_SCALAR(inst);
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xc->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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cacheCompletionEvent
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.unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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// if we have a cache, do cache access too
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~UNCACHEABLE;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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}
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}
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::read(Addr addr, double& data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, float& data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->write(memReq, data);
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Write;
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memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~UNCACHEABLE;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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}
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}
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if (res && (fault == No_Fault))
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*res = memReq->result;
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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#ifdef FULL_SYSTEM
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Addr
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SimpleCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(xc, addr);
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}
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#endif // FULL_SYSTEM
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Tick save_cycle = 0;
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void
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SimpleCPU::processCacheCompletion()
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{
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switch (status()) {
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case IcacheMissStall:
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icacheStallCycles += curTick - lastIcacheStall;
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_status = IcacheMissComplete;
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scheduleTickEvent(1);
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break;
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case DcacheMissStall:
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dcacheStallCycles += curTick - lastDcacheStall;
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_status = Running;
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scheduleTickEvent(1);
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break;
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case SwitchedOut:
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// If this CPU has been switched out due to sampling/warm-up,
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// ignore any further status changes (e.g., due to cache
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// misses outstanding at the time of the switch).
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return;
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default:
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panic("SimpleCPU::processCacheCompletion: bad state");
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break;
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}
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}
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|
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#ifdef FULL_SYSTEM
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void
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SimpleCPU::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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if (xc->status() == ExecContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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xc->activate();
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Annotate::Resume(xc);
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}
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}
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#endif // FULL_SYSTEM
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/* start simulation, program loaded, processor precise state initialized */
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void
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SimpleCPU::tick()
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{
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traceData = NULL;
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|
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Fault fault = No_Fault;
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|
|
#ifdef FULL_SYSTEM
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if (AlphaISA::check_interrupts &&
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xc->cpu->check_interrupts() &&
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!PC_PAL(xc->regs.pc) &&
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status() != IcacheMissComplete) {
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int ipl = 0;
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int summary = 0;
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AlphaISA::check_interrupts = 0;
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IntReg *ipr = xc->regs.ipr;
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if (xc->regs.ipr[TheISA::IPR_SIRR]) {
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for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
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i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
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if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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|
|
uint64_t interrupts = xc->cpu->intr_status();
|
|
for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
|
|
i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
|
|
if (ipr[TheISA::IPR_ASTRR])
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
|
|
ipr[TheISA::IPR_ISR] = summary;
|
|
ipr[TheISA::IPR_INTID] = ipl;
|
|
xc->ev5_trap(Interrupt_Fault);
|
|
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
ipr[TheISA::IPR_IPLR], ipl, summary);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// maintain $r0 semantics
|
|
xc->regs.intRegFile[ZeroReg] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
xc->regs.floatRegFile.d[ZeroReg] = 0.0;
|
|
#endif // TARGET_ALPHA
|
|
|
|
if (status() == IcacheMissComplete) {
|
|
// We've already fetched an instruction and were stalled on an
|
|
// I-cache miss. No need to fetch it again.
|
|
|
|
// Set status to running; tick event will get rescheduled if
|
|
// necessary at end of tick() function.
|
|
_status = Running;
|
|
}
|
|
else {
|
|
// Try to fetch an instruction
|
|
|
|
// set up memory request for instruction fetch
|
|
#ifdef FULL_SYSTEM
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
#else
|
|
#define IFETCH_FLAGS(pc) 0
|
|
#endif
|
|
|
|
memReq->cmd = Read;
|
|
memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
|
|
IFETCH_FLAGS(xc->regs.pc));
|
|
|
|
fault = xc->translateInstReq(memReq);
|
|
|
|
if (fault == No_Fault)
|
|
fault = xc->mem->read(memReq, inst);
|
|
|
|
if (icacheInterface && fault == No_Fault) {
|
|
memReq->completionEvent = NULL;
|
|
|
|
memReq->time = curTick;
|
|
memReq->flags &= ~UNCACHEABLE;
|
|
MemAccessResult result = icacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && icacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastIcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = IcacheMissStall;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
// If we've got a valid instruction (i.e., no fault on instruction
|
|
// fetch), then execute it.
|
|
if (fault == No_Fault) {
|
|
|
|
// keep an instruction count
|
|
numInst++;
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
// decode the instruction
|
|
StaticInstPtr<TheISA> si(inst);
|
|
|
|
traceData = Trace::getInstRecord(curTick, xc, this, si,
|
|
xc->regs.pc);
|
|
|
|
#ifdef FULL_SYSTEM
|
|
xc->regs.opcode = (inst >> 26) & 0x3f;
|
|
xc->regs.ra = (inst >> 21) & 0x1f;
|
|
#endif // FULL_SYSTEM
|
|
|
|
xc->func_exe_inst++;
|
|
|
|
fault = si->execute(this, xc, traceData);
|
|
#ifdef FS_MEASURE
|
|
if (!(xc->misspeculating()) && (xc->system->bin)) {
|
|
SWContext *ctx = xc->swCtx;
|
|
if (ctx && !ctx->callStack.empty()) {
|
|
if (si->isCall()) {
|
|
ctx->calls++;
|
|
}
|
|
if (si->isReturn()) {
|
|
if (ctx->calls == 0) {
|
|
fnCall *top = ctx->callStack.top();
|
|
DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
|
|
delete top;
|
|
ctx->callStack.pop();
|
|
if (ctx->callStack.empty())
|
|
xc->system->nonPath->activate();
|
|
else
|
|
ctx->callStack.top()->myBin->activate();
|
|
|
|
xc->system->dumpState(xc);
|
|
} else {
|
|
ctx->calls--;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
if (si->isMemRef()) {
|
|
numMemRefs++;
|
|
}
|
|
|
|
if (si->isLoad()) {
|
|
++numLoad;
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
}
|
|
|
|
if (traceData)
|
|
traceData->finalize();
|
|
|
|
} // if (fault == No_Fault)
|
|
|
|
if (fault != No_Fault) {
|
|
#ifdef FULL_SYSTEM
|
|
xc->ev5_trap(fault);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
else {
|
|
// go to the next instruction
|
|
xc->regs.pc = xc->regs.npc;
|
|
xc->regs.npc += sizeof(MachInst);
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
Addr oldpc;
|
|
do {
|
|
oldpc = xc->regs.pc;
|
|
system->pcEventQueue.service(xc);
|
|
} while (oldpc != xc->regs.pc);
|
|
#endif
|
|
|
|
assert(status() == Running ||
|
|
status() == Idle ||
|
|
status() == DcacheMissStall);
|
|
|
|
if (status() == Running && !tickEvent.scheduled())
|
|
tickEvent.schedule(curTick + 1);
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// SimpleCPU Simulation Object
|
|
//
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
SimObjectParam<AlphaItb *> itb;
|
|
SimObjectParam<AlphaDtb *> dtb;
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
SimObjectParam<System *> system;
|
|
Param<int> mult;
|
|
#else
|
|
SimObjectParam<Process *> workload;
|
|
#endif // FULL_SYSTEM
|
|
|
|
SimObjectParam<BaseMem *> icache;
|
|
SimObjectParam<BaseMem *> dcache;
|
|
|
|
Param<bool> defer_registration;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
|
"terminate when any thread reaches this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
|
"terminate when all threads have reached this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
|
"terminate when any thread reaches this load count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
|
"terminate when all threads have reached this load count",
|
|
0),
|
|
|
|
#ifdef FULL_SYSTEM
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
INIT_PARAM(mem, "memory"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
|
|
#else
|
|
INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
|
INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
|
|
INIT_PARAM_DFLT(defer_registration, "defer registration with system "
|
|
"(for sampling)", false)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
SimpleCPU *cpu;
|
|
#ifdef FULL_SYSTEM
|
|
if (mult != 1)
|
|
panic("processor clock multiplier must be 1\n");
|
|
|
|
cpu = new SimpleCPU(getInstanceName(), system,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
max_loads_any_thread, max_loads_all_threads,
|
|
itb, dtb, mem,
|
|
(icache) ? icache->getInterface() : NULL,
|
|
(dcache) ? dcache->getInterface() : NULL,
|
|
ticksPerSecond * mult);
|
|
#else
|
|
|
|
cpu = new SimpleCPU(getInstanceName(), workload,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
max_loads_any_thread, max_loads_all_threads,
|
|
(icache) ? icache->getInterface() : NULL,
|
|
(dcache) ? dcache->getInterface() : NULL);
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
if (!defer_registration) {
|
|
cpu->registerExecContexts();
|
|
}
|
|
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
|
|
|