80d9be86e6
Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
168 lines
4.6 KiB
C++
168 lines
4.6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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*/
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#ifndef __ARCH_ALPHA_UTILITY_HH__
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#define __ARCH_ALPHA_UTILITY_HH__
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#include "arch/alpha/types.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/regfile.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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namespace AlphaISA {
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uint64_t getArgument(ThreadContext *tc, int number, bool fp);
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inline bool
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inUserMode(ThreadContext *tc)
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{
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return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
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}
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inline bool
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isCallerSaveIntegerRegister(unsigned int reg)
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{
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
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}
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inline bool
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isCalleeSaveIntegerRegister(unsigned int reg)
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{
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panic("register classification not implemented");
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return reg >= 9 && reg <= 15;
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}
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inline bool
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isCallerSaveFloatRegister(unsigned int reg)
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{
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panic("register classification not implemented");
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return false;
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}
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inline bool
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isCalleeSaveFloatRegister(unsigned int reg)
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{
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panic("register classification not implemented");
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return false;
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}
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inline Addr
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alignAddress(const Addr &addr, unsigned int nbytes)
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{
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return (addr & ~(nbytes - 1));
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}
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// Instruction address compression hooks
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inline Addr
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realPCToFetchPC(const Addr &addr)
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{
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return addr;
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}
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inline Addr
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fetchPCToRealPC(const Addr &addr)
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{
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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inline size_t
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fetchInstSize()
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{
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return sizeof(MachInst);
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}
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inline MachInst
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makeRegisterCopy(int dest, int src)
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{
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panic("makeRegisterCopy not implemented");
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return 0;
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}
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// Machine operations
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void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum);
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void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum);
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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// Alpha IPR register accessors
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inline bool PcPAL(Addr addr) { return addr & 0x3; }
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inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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// User Virtual
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inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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// Kernel Direct Mapped
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inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
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inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
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// Kernel Virtual
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inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
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inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(PageBytes - 1); }
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inline Addr
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RoundPage(Addr addr)
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{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
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void initIPRs(ThreadContext *tc, int cpuId);
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#if FULL_SYSTEM
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void initCPU(ThreadContext *tc, int cpuId);
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/**
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* Function to check for and process any interrupts.
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* @param tc The thread context.
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*/
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template <class TC>
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void processInterrupts(TC *tc);
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#endif
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_UTILITY_HH__
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