89596f0cfa
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
33 lines
1.4 KiB
C
33 lines
1.4 KiB
C
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sdw' : ('signed int', 64),
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'udw' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
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'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
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'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
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#'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
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#'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
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#'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
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'Mem': MemOperandTraits('udw', None,
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('IsMemRef', 'IsLoad', 'IsStore'), 4)
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#'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
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#'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
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#'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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#'R0': IntRegOperandTraits('uq', '0', None, 1),
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#'R16': IntRegOperandTraits('uq', '16', None, 1)
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}};
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