373 lines
11 KiB
C++
373 lines
11 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
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#define __ARCH_ALPHA_ISA_TRAITS_HH__
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namespace LittleEndianGuest {}
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using namespace LittleEndianGuest;
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//#include "arch/alpha/faults.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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#include "sim/faults.hh"
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class ExecContext;
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class FastCPU;
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class FullCPU;
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class Checkpoint;
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#define TARGET_ALPHA
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class StaticInst;
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class StaticInstPtr;
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namespace EV5 {
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int DTB_ASN_ASN(uint64_t reg);
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int ITB_ASN_ASN(uint64_t reg);
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}
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namespace AlphaISA
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{
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typedef uint32_t MachInst;
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typedef uint8_t RegIndex;
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enum {
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MemoryEnd = 0xffffffffffffffffULL,
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NumIntRegs = 32,
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NumFloatRegs = 32,
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// @todo: Figure out what this number really should be.
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NumMiscRegs = 32,
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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MaxInstSrcRegs = 3,
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MaxInstDestRegs = 2,
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// semantically meaningful register indices
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ZeroReg = 31, // architecturally meaningful
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// the rest of these depend on the ABI
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StackPointerReg = 30,
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GlobalPointerReg = 29,
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ProcedureValueReg = 27,
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ReturnAddressReg = 26,
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ReturnValueReg = 0,
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FramePointerReg = 15,
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ArgumentReg0 = 16,
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ArgumentReg1 = 17,
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ArgumentReg2 = 18,
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ArgumentReg3 = 19,
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ArgumentReg4 = 20,
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ArgumentReg5 = 21,
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LogVMPageSize = 13, // 8K bytes
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VMPageSize = (1 << LogVMPageSize),
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BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
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WordBytes = 4,
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HalfwordBytes = 2,
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ByteBytes = 1,
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DepNA = 0,
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};
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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// 0..31 are the integer regs 0..31
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// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
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FP_Base_DepTag = 32,
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Ctrl_Base_DepTag = 64,
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Fpcr_DepTag = 64, // floating point control register
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Uniq_DepTag = 65,
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Lock_Flag_DepTag = 66,
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Lock_Addr_DepTag = 67,
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IPR_Base_DepTag = 68
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};
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typedef uint64_t IntReg;
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typedef IntReg IntRegFile[NumIntRegs];
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// floating point register file entry type
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typedef union {
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uint64_t q;
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double d;
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} FloatReg;
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typedef union {
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uint64_t q[NumFloatRegs]; // integer qword view
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double d[NumFloatRegs]; // double-precision floating point view
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} FloatRegFile;
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extern const Addr PageShift;
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extern const Addr PageBytes;
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extern const Addr PageMask;
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extern const Addr PageOffset;
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#if FULL_SYSTEM
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typedef uint64_t InternalProcReg;
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#include "arch/alpha/isa_fullsys_traits.hh"
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#else
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enum {
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NumInternalProcRegs = 0
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};
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#endif
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// control register file contents
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typedef uint64_t MiscReg;
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class MiscRegFile {
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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public:
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MiscReg readReg(int misc_reg);
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
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Fault setReg(int misc_reg, const MiscReg &val);
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc);
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#if FULL_SYSTEM
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void clearIprs();
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protected:
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
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Fault setIpr(int idx, uint64_t val, ExecContext *xc);
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#endif
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friend class RegFile;
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};
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enum {
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TotalNumRegs =
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NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
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};
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enum {
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TotalDataRegs = NumIntRegs + NumFloatRegs
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};
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typedef union {
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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struct RegFile {
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegs; // control register file
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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#if FULL_SYSTEM
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IntReg palregs[NumIntRegs]; // PAL shadow registers
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int intrflag; // interrupt flag
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bool pal_shadow; // using pal_shadow registers
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inline int instAsid()
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{ return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
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inline int dataAsid()
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{ return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
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#endif // FULL_SYSTEM
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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StaticInstPtr decodeInst(MachInst);
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// return a no-op instruction... used for instruction fetch faults
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extern const MachInst NoopMachInst;
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enum annotes {
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ANNOTE_NONE = 0,
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// An impossible number for instruction annotations
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ITOUCH_ANNOTE = 0xffffffff,
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};
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static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
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}
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static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 9 && reg <= 15);
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}
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static inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline Addr alignAddress(const Addr &addr,
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unsigned int nbytes) {
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return (addr & ~(nbytes - 1));
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}
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// Instruction address compression hooks
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static inline Addr realPCToFetchPC(const Addr &addr) {
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return addr;
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}
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static inline Addr fetchPCToRealPC(const Addr &addr) {
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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static inline size_t fetchInstSize() {
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return sizeof(MachInst);
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}
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static inline MachInst makeRegisterCopy(int dest, int src) {
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panic("makeRegisterCopy not implemented");
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return 0;
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}
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// Machine operations
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void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
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int regnum);
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void restoreMachineReg(RegFile ®s, const AnyReg ®,
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int regnum);
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#if 0
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static void serializeSpecialRegs(const Serializable::Proxy &proxy,
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const RegFile ®s);
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static void unserializeSpecialRegs(const IniFile *db,
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const std::string &category,
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ConfigNode *node,
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RegFile ®s);
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#endif
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param xc The execution context.
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*/
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template <class XC>
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void zeroRegisters(XC *xc);
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//typedef AlphaISA TheISA;
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//typedef TheISA::MachInst MachInst;
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//typedef TheISA::Addr Addr;
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//typedef TheISA::RegIndex RegIndex;
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//typedef TheISA::IntReg IntReg;
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//typedef TheISA::IntRegFile IntRegFile;
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//typedef TheISA::FloatReg FloatReg;
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//typedef TheISA::FloatRegFile FloatRegFile;
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//typedef TheISA::MiscReg MiscReg;
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//typedef TheISA::MiscRegFile MiscRegFile;
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//typedef TheISA::AnyReg AnyReg;
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//typedef TheISA::RegFile RegFile;
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//const int NumIntRegs = TheISA::NumIntRegs;
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//const int NumFloatRegs = TheISA::NumFloatRegs;
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//const int NumMiscRegs = TheISA::NumMiscRegs;
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//const int TotalNumRegs = TheISA::TotalNumRegs;
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//const int VMPageSize = TheISA::VMPageSize;
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//const int LogVMPageSize = TheISA::LogVMPageSize;
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//const int ZeroReg = TheISA::ZeroReg;
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//const int StackPointerReg = TheISA::StackPointerReg;
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//const int GlobalPointerReg = TheISA::GlobalPointerReg;
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//const int ReturnAddressReg = TheISA::ReturnAddressReg;
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//const int ReturnValueReg = TheISA::ReturnValueReg;
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//const int ArgumentReg0 = TheISA::ArgumentReg0;
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//const int ArgumentReg1 = TheISA::ArgumentReg1;
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//const int ArgumentReg2 = TheISA::ArgumentReg2;
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//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
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const Addr MaxAddr = (Addr)-1;
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};
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#if !FULL_SYSTEM
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class SyscallReturn {
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint64_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint64_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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#endif
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#if FULL_SYSTEM
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//typedef TheISA::InternalProcReg InternalProcReg;
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//const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
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//const int NumInterruptLevels = TheISA::NumInterruptLevels;
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#include "arch/alpha/ev5.hh"
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#endif
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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