89060f1fd8
Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic.
138 lines
4.6 KiB
C++
138 lines
4.6 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Gabe Black
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*/
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#ifndef __ARM_FAULTS_HH__
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#define __ARM_FAULTS_HH__
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#include "arch/arm/types.hh"
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#include "config/full_system.hh"
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#include "sim/faults.hh"
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// The design of the "name" and "vect" functions is in sim/faults.hh
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namespace ArmISA
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{
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typedef const Addr FaultOffset;
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class ArmFaultBase : public FaultBase
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{
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protected:
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Addr getVector(ThreadContext *tc);
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public:
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struct FaultVals
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{
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const FaultName name;
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const FaultOffset offset;
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const OperatingMode nextMode;
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const uint8_t armPcOffset;
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const uint8_t thumbPcOffset;
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const bool abortDisable;
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const bool fiqDisable;
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FaultStat count;
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};
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#if FULL_SYSTEM
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void invoke(ThreadContext *tc);
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#endif
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virtual FaultStat& countStat() = 0;
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virtual FaultOffset offset() = 0;
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virtual OperatingMode nextMode() = 0;
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virtual uint8_t armPcOffset() = 0;
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virtual uint8_t thumbPcOffset() = 0;
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virtual bool abortDisable() = 0;
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virtual bool fiqDisable() = 0;
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};
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template<typename T>
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class ArmFault : public ArmFaultBase
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{
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protected:
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static FaultVals vals;
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public:
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FaultName name() const { return vals.name; }
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FaultStat & countStat() {return vals.count;}
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FaultOffset offset() { return vals.offset; }
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OperatingMode nextMode() { return vals.nextMode; }
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uint8_t armPcOffset() { return vals.armPcOffset; }
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uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
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bool abortDisable() { return vals.abortDisable; }
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bool fiqDisable() { return vals.fiqDisable; }
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};
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class Reset : public ArmFault<Reset> {};
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class UndefinedInstruction : public ArmFault<UndefinedInstruction>
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{
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#if !FULL_SYSTEM
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protected:
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ExtMachInst machInst;
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bool unknown;
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const char *mnemonic;
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public:
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UndefinedInstruction(ExtMachInst _machInst,
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bool _unknown,
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const char *_mnemonic = NULL) :
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machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic)
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{
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}
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void invoke(ThreadContext *tc);
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#endif
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};
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class SupervisorCall : public ArmFault<SupervisorCall> {};
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class PrefetchAbort : public ArmFault<PrefetchAbort> {};
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class DataAbort : public ArmFault<DataAbort> {};
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class Interrupt : public ArmFault<Interrupt> {};
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class FastInterrupt : public ArmFault<FastInterrupt> {};
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} // ArmISA namespace
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#endif // __ARM_FAULTS_HH__
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