ae1652b813
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU.
794 lines
88 KiB
Plaintext
794 lines
88 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000015 # Number of seconds simulated
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sim_ticks 14993500 # Number of ticks simulated
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final_tick 14993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 32330 # Simulator instruction rate (inst/s)
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host_op_rate 32329 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 38030689 # Simulator tick rate (ticks/s)
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host_mem_usage 224252 # Number of bytes of host memory used
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host_seconds 0.39 # Real time elapsed on the host
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sim_insts 12745 # Number of instructions simulated
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62336 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 974 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2659285690 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1498249241 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4157534932 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2659285690 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2659285690 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2659285690 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1498249241 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4157534932 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4043 # DTB read hits
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system.cpu.dtb.read_misses 104 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4147 # DTB read accesses
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system.cpu.dtb.write_hits 2093 # DTB write hits
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system.cpu.dtb.write_misses 65 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 2158 # DTB write accesses
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system.cpu.dtb.data_hits 6136 # DTB hits
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system.cpu.dtb.data_misses 169 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 6305 # DTB accesses
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system.cpu.itb.fetch_hits 5063 # ITB hits
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system.cpu.itb.fetch_misses 68 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 5131 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload0.num_syscalls 17 # Number of system calls
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system.cpu.workload1.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 29988 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 6234 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 3551 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1730 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 4726 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 185 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 34888 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6234 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1621 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 5843 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1806 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 5063 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 763 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 24485 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.424872 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.811431 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 18642 76.14% 76.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 463 1.89% 78.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 348 1.42% 79.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 451 1.84% 81.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 433 1.77% 83.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 338 1.38% 84.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 497 2.03% 86.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 532 2.17% 88.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2781 11.36% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 24485 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.207883 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.163399 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 35160 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 5629 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 5043 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 481 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 2441 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 657 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 429 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 30497 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 762 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 2441 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 35832 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2821 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 862 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 4769 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 2029 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 28347 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
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system.cpu.rename.LSQFullEvents 2069 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 21319 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 35425 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 35391 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 12179 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 54 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 5554 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2631 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1322 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.memDep1.insertedLoads 2538 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep1.insertedStores 1270 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep1.conflictingLoads 13 # Number of conflicting loads.
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system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 25174 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 21355 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 11204 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 6343 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 24485 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.872167 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.446196 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 15521 63.39% 63.39% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 3217 13.14% 76.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 2370 9.68% 86.21% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 1453 5.93% 92.14% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 1034 4.22% 96.37% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 556 2.27% 98.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 237 0.97% 99.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 75 0.31% 99.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 22 0.09% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 24485 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 11 6.18% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 104 58.43% 64.61% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 63 35.39% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 7361 67.94% 67.96% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.97% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 2308 21.30% 89.29% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1160 10.71% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 10834 # Type of FU issued
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system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.FU_type_1::IntAlu 7172 68.17% 68.19% # Type of FU issued
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system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.20% # Type of FU issued
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system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.20% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.22% # Type of FU issued
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system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2223 21.13% 89.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1121 10.65% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 10521 # Type of FU issued
|
|
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntAlu 14533 68.05% 68.07% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntMult 2 0.01% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntDiv 0 0.00% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatMult 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMult 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShift 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemRead 4531 21.22% 89.32% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemWrite 2281 10.68% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::total 21355 # Type of FU issued
|
|
system.cpu.iq.rate 0.712118 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 95 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 83 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 178 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.004449 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.003887 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.008335 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 67413 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 36435 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 19171 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 21507 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 457 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1355 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 573 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 25387 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 653 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 5169 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2592 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1220 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20001 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2104 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2055 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4159 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1354 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 84 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 78 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 162 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3212 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 3127 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6339 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1650 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1625 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 3275 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1108 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1072 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2180 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.666967 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9882 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 9596 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 19478 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9755 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 9436 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 19191 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 5007 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 4861 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 9868 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6484 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 6279 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 12763 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate::0 0.325297 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.314659 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.639956 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.772209 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.774168 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.773172 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 12568 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1309 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 24431 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.523065 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.302863 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 18816 77.02% 77.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 2827 11.57% 88.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1198 4.90% 93.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 508 2.08% 95.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 350 1.43% 97.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 244 1.00% 98.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 205 0.84% 98.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 82 0.34% 99.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 201 0.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 24431 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 201 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 117663 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 53150 # The number of ROB writes
|
|
system.cpu.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5503 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
|
system.cpu.cpi::0 4.706215 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 4.705476 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.352923 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.212485 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.212518 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.425003 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 25299 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 14501 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.tagsinuse 314.927989 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 4192 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 6.707200 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 314.927989 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.153773 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.153773 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4192 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4192 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4192 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4192 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4192 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4192 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 871 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 871 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 871 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 871 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 871 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 871 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34167000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 34167000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 34167000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 34167000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 34167000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 34167000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5063 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5063 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5063 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5063 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5063 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5063 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.172032 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.172032 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.172032 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.172032 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.172032 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.172032 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39227.324914 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 39227.324914 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 39227.324914 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 39227.324914 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24783500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 24783500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24783500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 24783500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24783500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 24783500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.123445 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.123445 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.123445 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39653.600000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39653.600000 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 215.917106 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 4606 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 13.160000 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 215.917106 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.052714 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.052714 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3594 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3594 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4606 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4606 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4606 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4606 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1042 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1042 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1042 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1042 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 14022500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 28872500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 28872500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 42895000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 42895000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 42895000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 42895000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3918 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3918 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5648 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5648 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5648 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5648 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082695 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.082695 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.184490 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.184490 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.184490 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.184490 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43279.320988 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 43279.320988 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40212.395543 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 40212.395543 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 41166.026871 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 41166.026871 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 691 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 691 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9453500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9453500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6369000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6369000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15822500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 15822500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15822500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 15822500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052323 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062146 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.062146 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062146 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.062146 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46114.634146 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46114.634146 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43623.287671 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43623.287671 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45078.347578 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45078.347578 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45078.347578 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45078.347578 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 435.815079 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 827 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002418 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 315.212279 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 120.602800 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.009620 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003681 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.013300 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 623 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 623 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 623 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 974 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24119500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9201500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 33321000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6205000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6205000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 24119500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 15406500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 39526000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 24119500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 15406500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 39526000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996800 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996800 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996800 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38715.088283 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 44885.365854 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 40242.753623 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42500 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42500 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38715.088283 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 40581.108830 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38715.088283 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 40581.108830 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 10 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3750 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22168000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8579500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30747500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5752000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5752000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22168000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14331500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 36499500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22168000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14331500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 36499500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35582.664526 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41851.219512 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37134.661836 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39397.260274 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39397.260274 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|