ae1652b813
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU.
630 lines
71 KiB
Plaintext
630 lines
71 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 11763500 # Number of ticks simulated
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final_tick 11763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 53396 # Simulator instruction rate (inst/s)
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host_op_rate 53387 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 108411505 # Simulator tick rate (ticks/s)
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host_mem_usage 219412 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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sim_insts 5792 # Number of instructions simulated
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sim_ops 5792 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28928 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 452 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1909635738 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 549496323 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2459132061 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1909635738 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1909635738 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1909635738 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 549496323 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2459132061 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 9 # Number of system calls
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system.cpu.numCycles 23528 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2457 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 2014 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 2037 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 618 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 7380 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14306 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2457 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 778 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2377 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1402 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 936 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 1859 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 11638 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.229249 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.662964 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 9261 79.58% 79.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 173 1.49% 81.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 162 1.39% 82.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 137 1.18% 83.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 198 1.70% 85.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 148 1.27% 86.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 250 2.15% 88.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 106 0.91% 89.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1203 10.34% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 11638 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.104429 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.608041 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 7505 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 1074 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2213 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 784 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 351 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 12646 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 784 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 7717 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 446 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 386 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 2059 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 246 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 11999 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 10316 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 19600 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 19545 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 5318 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 543 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2051 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1909 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 10820 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 9196 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 160 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 4794 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 4145 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 11638 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.790170 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.525459 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 8215 70.59% 70.59% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1109 9.53% 80.12% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 778 6.68% 86.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 515 4.43% 91.23% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 472 4.06% 95.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 322 2.77% 98.05% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 140 1.20% 99.25% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 48 0.41% 99.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 11638 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 4 2.34% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 75 43.86% 46.20% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 5661 61.56% 61.56% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.56% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 1833 19.93% 81.51% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1700 18.49% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 9196 # Type of FU issued
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system.cpu.iq.rate 0.390853 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.018595 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 30299 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 15649 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 8318 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 1090 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 863 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 784 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 229 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 10884 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 101 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 2051 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 1909 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8699 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1698 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 497 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3253 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1376 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1555 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.369730 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8502 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8345 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 4327 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 6939 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.354684 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.623577 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5101 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.316329 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 8424 77.61% 77.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1042 9.60% 87.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 639 5.89% 93.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 261 2.40% 95.50% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 182 1.68% 97.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 104 0.96% 98.14% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 67 0.62% 98.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 41 0.38% 99.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 94 0.87% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2007 # Number of memory references committed
|
|
system.cpu.commit.loads 961 # Number of loads committed
|
|
system.cpu.commit.membars 7 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1037 # Number of branches committed
|
|
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 21653 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 22571 # The number of ROB writes
|
|
system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 11890 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
|
|
system.cpu.cpi 4.062155 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 4.062155 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.246175 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.246175 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 13809 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7224 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 172.502715 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1427 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 4.008427 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 172.502715 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.084230 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.084230 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1427 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1427 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1427 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1427 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1427 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1427 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 432 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16299000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16299000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16299000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16299000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16299000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16299000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1859 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1859 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1859 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1859 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1859 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1859 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232383 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.232383 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.232383 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.232383 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.232383 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.232383 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 37729.166667 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 37729.166667 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 76 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 76 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 76 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 76 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13111000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 13111000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13111000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 13111000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13111000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 13111000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.191501 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.191501 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 63.218136 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2196 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 21.742574 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 63.218136 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.015434 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.015434 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2196 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2196 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2196 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2196 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 420 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12824500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 12824500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 16557000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 16557000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 16557000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 16557000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1570 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1570 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2616 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2616 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2616 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2616 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.057962 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.057962 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.160550 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.160550 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.160550 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.160550 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38980.243161 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38980.243161 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 39421.428571 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 39421.428571 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2168500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2168500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2086000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4254500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 4254500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4254500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 4254500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034395 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034395 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.038609 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.038609 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40157.407407 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40157.407407 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44382.978723 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44382.978723 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 203.045072 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 171.614713 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31.430359 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005237 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.006196 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 5 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 452 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12737500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2108500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 14846000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2028500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2028500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 12737500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 4137000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 16874500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 12737500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 4137000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 16874500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36289.173789 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39046.296296 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36656.790123 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43159.574468 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43159.574468 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 37332.964602 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 37332.964602 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11613500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1942500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13556000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1882000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1882000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11613500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3824500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15438000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11613500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3824500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15438000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|