gem5/src/arch
Gabe Black f57c286d2c O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
2008-10-09 00:09:26 -07:00
..
alpha alpha: Need to include cstring so that g++ 4.3 works. 2008-09-29 07:15:30 -07:00
mips O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. 2008-10-09 00:09:26 -07:00
sparc gcc: Add extra parens to quell warnings. 2008-09-27 21:03:49 -07:00
x86 X86: Fix the debugging microops. The debug functions can't handle a string object format. 2008-10-09 00:05:39 -07:00
isa_parser.py style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
isa_specific.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
micro_asm.py Microcode: Fix a silent typo error in the microcode assembler. 2008-10-09 00:07:38 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. 2007-11-08 18:51:50 -08:00