Andreas Hansson 88554790c3 Mem: Use cycles to express cache-related latencies ... This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency. The stat blocked_cycles that actually counter in ticks is now updated to count in cycles. As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.		2012-10-15 08:10:54 -04:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	Regression: Use CPU clock and 32-byte width for L1-L2 bus	2012-10-15 08:08:08 -04:00
Caches.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	AddrRange: Simplify AddrRange params Python hierarchy	2012-09-19 06:15:41 -04:00
O3_ARM_v7a.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
Options.py	se.py: support specifying multiple programs via command line	2012-09-09 09:33:45 -05:00
Simulation.py	Standard Switch: Drain the system before switching CPUs	2012-09-12 21:41:37 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00