Andreas Hansson c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations ... This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.		2013-01-31 07:49:14 -05:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	Regression: Use CPU clock and 32-byte width for L1-L2 bus	2012-10-15 08:08:08 -04:00
Caches.py	config: Unify caches used in regressions and adjust L2 MSHRs	2012-10-30 07:44:08 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	mem: Add DDR3 and LPDDR2 DRAM controller configurations	2013-01-31 07:49:14 -05:00
O3_ARM_v7a.py	branch predictor: move out of o3 and inorder cpus	2013-01-24 12:28:51 -06:00
Options.py	config: Fix description of checkpoint option from cycle to tick	2012-11-19 11:21:09 -05:00
Simulation.py	config: Fix issue with changeset: a4739b6f799d.	2013-01-08 17:12:22 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00