gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
Nilay Vaish fa1fbcf020 stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
2014-09-01 16:55:52 -05:00

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99 KiB
JSON

{
"name": null,
"sim_quantum": 0,
"system": {
"bridge": {
"slave": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"name": "bridge",
"req_size": 16,
"delay": 5.0000000000000004e-08,
"eventq_index": 0,
"master": {
"peer": "system.iobus.slave[0]",
"role": "MASTER"
},
"cxx_class": "Bridge",
"path": "system.bridge",
"resp_size": 16,
"type": "Bridge"
},
"l2c": {
"assoc": 8,
"mem_side": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"cpu_side": {
"peer": "system.toL2Bus.master[0]",
"role": "SLAVE"
},
"name": "l2c",
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 20,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"path": "system.l2c.tags",
"block_size": 64,
"type": "LRU",
"size": 4194304
},
"hit_latency": 20,
"mshrs": 20,
"response_latency": 20,
"is_top_level": false,
"tgts_per_mshr": 12,
"sequential_access": false,
"max_miss_count": 0,
"eventq_index": 0,
"prefetch_on_access": false,
"cxx_class": "BaseCache",
"path": "system.l2c",
"write_buffers": 8,
"two_queue": false,
"type": "BaseCache",
"forward_snoops": true,
"size": 4194304
},
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.apicbridge.master",
"system.system_port",
"system.l2c.mem_side",
"system.cpu0.interrupts.int_master",
"system.iocache.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"badaddr_responder": {
"ret_data8": 255,
"name": "badaddr_responder",
"pio": {
"peer": "system.membus.default",
"role": "SLAVE"
},
"ret_bad_addr": true,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.membus.badaddr_responder",
"pio_addr": 0,
"type": "IsaFake",
"ret_data16": 65535
},
"default": {
"peer": "system.membus.badaddr_responder.pio",
"role": "MASTER"
},
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.bridge.slave",
"system.cpu0.interrupts.pio",
"system.cpu0.interrupts.int_slave",
"system.physmem.port"
],
"role": "MASTER"
},
"cxx_class": "CoherentBus",
"path": "system.membus",
"type": "CoherentBus",
"use_default_range": false
},
"iobus": {
"slave": {
"peer": [
"system.bridge.master",
"system.pc.south_bridge.ide.dma",
"system.pc.south_bridge.io_apic.int_master"
],
"role": "SLAVE"
},
"name": "iobus",
"default": {
"peer": "system.pc.pciconfig.pio",
"role": "MASTER"
},
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.apicbridge.slave",
"system.pc.south_bridge.cmos.pio",
"system.pc.south_bridge.dma1.pio",
"system.pc.south_bridge.ide.pio",
"system.pc.south_bridge.ide.config",
"system.pc.south_bridge.keyboard.pio",
"system.pc.south_bridge.pic1.pio",
"system.pc.south_bridge.pic2.pio",
"system.pc.south_bridge.pit.pio",
"system.pc.south_bridge.speaker.pio",
"system.pc.south_bridge.io_apic.pio",
"system.pc.i_dont_exist.pio",
"system.pc.behind_pci.pio",
"system.pc.com_1.pio",
"system.pc.fake_com_2.pio",
"system.pc.fake_com_3.pio",
"system.pc.fake_com_4.pio",
"system.pc.fake_floppy.pio",
"system.iocache.cpu_side"
],
"role": "MASTER"
},
"cxx_class": "NoncoherentBus",
"path": "system.iobus",
"type": "NoncoherentBus",
"use_default_range": false
},
"physmem": [
{
"static_frontend_latency": 1e-08,
"tRFC": 2.6e-07,
"activation_limit": 4,
"tWTR": 7.500000000000001e-09,
"write_low_thresh_perc": 50,
"channels": 1,
"write_buffer_size": 64,
"device_bus_width": 8,
"write_high_thresh_perc": 85,
"cxx_class": "DRAMCtrl",
"null": false,
"port": {
"peer": "system.membus.master[3]",
"role": "SLAVE"
},
"in_addr_map": true,
"tRRD": 6.000000000000001e-09,
"tRTW": 2.5e-09,
"max_accesses_per_row": 16,
"burst_length": 8,
"tRTP": 7.500000000000001e-09,
"tWR": 1.5000000000000002e-08,
"eventq_index": 0,
"static_backend_latency": 1e-08,
"banks_per_rank": 8,
"addr_mapping": "RoRaBaChCo",
"tRCD": 1.375e-08,
"type": "DRAMCtrl",
"min_writes_per_switch": 16,
"ranks_per_channel": 2,
"page_policy": "open_adaptive",
"tCL": 1.375e-08,
"read_buffer_size": 32,
"conf_table_reported": true,
"tCK": 1.25e-09,
"tRAS": 3.5e-08,
"tBURST": 5e-09,
"path": "system.physmem",
"devices_per_rank": 8,
"name": "physmem",
"tXAW": 3.0000000000000004e-08,
"tREFI": 7.8e-06,
"mem_sched_policy": "frfcfs",
"tRP": 1.375e-08,
"device_rowbuffer_size": 1024
}
],
"apicbridge": {
"slave": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"name": "apicbridge",
"req_size": 16,
"delay": 5.0000000000000004e-08,
"eventq_index": 0,
"master": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"cxx_class": "Bridge",
"path": "system.apicbridge",
"resp_size": 16,
"type": "Bridge"
},
"intel_mp_table": {
"oem_table_addr": 0,
"name": "intel_mp_table",
"ext_entries": [
{
"parent_bus": 1,
"name": "ext_entries",
"type": "X86IntelMPBusHierarchy",
"subtractive_decode": true,
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::BusHierarchy",
"path": "system.intel_mp_table.ext_entries",
"bus_id": 0
}
],
"spec_rev": 4,
"eventq_index": 0,
"base_entries": [
{
"enable": true,
"local_apic_version": 20,
"name": "base_entries00",
"family": 0,
"local_apic_id": 0,
"bootstrap": true,
"feature_flags": 0,
"eventq_index": 0,
"stepping": 0,
"cxx_class": "X86ISA::IntelMP::Processor",
"path": "system.intel_mp_table.base_entries00",
"model": 0,
"type": "X86IntelMPProcessor"
},
{
"enable": true,
"name": "base_entries01",
"cxx_class": "X86ISA::IntelMP::IOAPIC",
"version": 17,
"eventq_index": 0,
"address": 4273995776,
"path": "system.intel_mp_table.base_entries01",
"type": "X86IntelMPIOAPIC",
"id": 1
},
{
"name": "base_entries02",
"type": "X86IntelMPBus",
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::Bus",
"path": "system.intel_mp_table.base_entries02",
"bus_id": 0
},
{
"name": "base_entries03",
"type": "X86IntelMPBus",
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::Bus",
"path": "system.intel_mp_table.base_entries03",
"bus_id": 1
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries04",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 16,
"path": "system.intel_mp_table.base_entries04",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 16
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries05",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries05",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 0
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries06",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 2,
"path": "system.intel_mp_table.base_entries06",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 0
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries07",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries07",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 1
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries08",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 1,
"path": "system.intel_mp_table.base_entries08",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 1
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries09",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries09",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 3
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries10",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 3,
"path": "system.intel_mp_table.base_entries10",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 3
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries11",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries11",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 4
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries12",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 4,
"path": "system.intel_mp_table.base_entries12",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 4
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries13",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries13",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 5
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries14",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 5,
"path": "system.intel_mp_table.base_entries14",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 5
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries15",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries15",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 6
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries16",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 6,
"path": "system.intel_mp_table.base_entries16",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 6
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries17",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries17",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 7
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries18",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 7,
"path": "system.intel_mp_table.base_entries18",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 7
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries19",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries19",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 8
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries20",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 8,
"path": "system.intel_mp_table.base_entries20",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 8
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries21",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries21",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 9
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries22",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 9,
"path": "system.intel_mp_table.base_entries22",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 9
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries23",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries23",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 10
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries24",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 10,
"path": "system.intel_mp_table.base_entries24",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 10
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries25",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries25",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 11
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries26",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 11,
"path": "system.intel_mp_table.base_entries26",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 11
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries27",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries27",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 12
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries28",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 12,
"path": "system.intel_mp_table.base_entries28",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 12
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries29",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries29",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 13
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries30",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 13,
"path": "system.intel_mp_table.base_entries30",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 13
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries31",
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries31",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 14
},
{
"polarity": "ConformPolarity",
"dest_io_apic_id": 1,
"name": "base_entries32",
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
"source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 14,
"path": "system.intel_mp_table.base_entries32",
"type": "X86IntelMPIOIntAssignment",
"source_bus_irq": 14
}
],
"cxx_class": "X86ISA::IntelMP::ConfigTable",
"path": "system.intel_mp_table",
"type": "X86IntelMPConfigTable",
"local_apic": 4276092928,
"oem_table_size": 0
},
"cxx_class": "LinuxX86System",
"load_offset": 0,
"work_end_ckpt_count": 0,
"smbios_table": {
"name": "smbios_table",
"structures": [
{
"major": 0,
"name": "structures",
"emb_cont_firmware_major": 0,
"rom_size": 0,
"starting_addr_segment": 0,
"emb_cont_firmware_minor": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::SMBios::BiosInformation",
"path": "system.smbios_table.structures",
"type": "X86SMBiosBiosInformation",
"minor": 0
}
],
"major_version": 2,
"minor_version": 5,
"eventq_index": 0,
"cxx_class": "X86ISA::SMBios::SMBiosTable",
"path": "system.smbios_table",
"type": "X86SMBiosSMBiosTable"
},
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"init_perf_level": 0,
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"pc": {
"fake_com_4": {
"ret_data8": 255,
"name": "fake_com_4",
"pio": {
"peer": "system.iobus.master[16]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.fake_com_4",
"pio_addr": 9223372036854776552,
"type": "IsaFake",
"ret_data16": 65535
},
"pciconfig": {
"name": "pciconfig",
"pio": {
"peer": "system.iobus.default",
"role": "SLAVE"
},
"bus": 0,
"pio_latency": 3.0000000000000004e-08,
"eventq_index": 0,
"cxx_class": "PciConfigAll",
"path": "system.pc.pciconfig",
"pio_addr": 0,
"type": "PciConfigAll",
"size": 16777216
},
"fake_com_2": {
"ret_data8": 255,
"name": "fake_com_2",
"pio": {
"peer": "system.iobus.master[14]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.fake_com_2",
"pio_addr": 9223372036854776568,
"type": "IsaFake",
"ret_data16": 65535
},
"name": "pc",
"south_bridge": {
"int_lines": [
{
"name": "int_lines0",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines0.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines0",
"type": "X86IntLine"
},
{
"name": "int_lines1",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines1.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines1",
"type": "X86IntLine"
},
{
"name": "int_lines2",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines2.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines2",
"type": "X86IntLine"
},
{
"name": "int_lines3",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines3.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines3",
"type": "X86IntLine"
},
{
"name": "int_lines4",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines4.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines4",
"type": "X86IntLine"
},
{
"name": "int_lines5",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 1,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines5.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines5",
"type": "X86IntLine"
},
{
"name": "int_lines6",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 12,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
"path": "system.pc.south_bridge.int_lines6.sink",
"type": "X86IntSinkPin"
},
"cxx_class": "X86ISA::IntLine",
"path": "system.pc.south_bridge.int_lines6",
"type": "X86IntLine"
}
],
"name": "south_bridge",
"speaker": {
"name": "speaker",
"pio": {
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "X86ISA::Speaker",
"path": "system.pc.south_bridge.speaker",
"pio_addr": 9223372036854775905,
"type": "PcSpeaker"
},
"keyboard": {
"command_port": 9223372036854775908,
"name": "keyboard",
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"mouse_int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.keyboard.mouse_int_pin",
"type": "X86IntSourcePin",
"name": "mouse_int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
"pio_latency": 1.0000000000000001e-07,
"keyboard_int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.keyboard.keyboard_int_pin",
"type": "X86IntSourcePin",
"name": "keyboard_int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
"eventq_index": 0,
"cxx_class": "X86ISA::I8042",
"path": "system.pc.south_bridge.keyboard",
"pio_addr": 0,
"data_port": 9223372036854775904,
"type": "I8042"
},
"pit": {
"name": "pit",
"pio": {
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.pit.int_pin",
"type": "X86IntSourcePin",
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "X86ISA::I8254",
"path": "system.pc.south_bridge.pit",
"pio_addr": 9223372036854775872,
"type": "I8254"
},
"io_apic": {
"int_master": {
"peer": "system.iobus.slave[2]",
"role": "MASTER"
},
"name": "io_apic",
"pio": {
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"apic_id": 1,
"int_latency": 1e-09,
"eventq_index": 0,
"cxx_class": "X86ISA::I82094AA",
"path": "system.pc.south_bridge.io_apic",
"pio_addr": 4273995776,
"type": "I82094AA"
},
"pic1": {
"name": "pic1",
"output": {
"eventq_index": 0,
"path": "system.pc.south_bridge.pic1.output",
"type": "X86IntSourcePin",
"name": "output",
"cxx_class": "X86ISA::IntSourcePin"
},
"pio": {
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"mode": "I8259Master",
"cxx_class": "X86ISA::I8259",
"path": "system.pc.south_bridge.pic1",
"pio_addr": 9223372036854775840,
"type": "I8259"
},
"pic2": {
"name": "pic2",
"output": {
"eventq_index": 0,
"path": "system.pc.south_bridge.pic2.output",
"type": "X86IntSourcePin",
"name": "output",
"cxx_class": "X86ISA::IntSourcePin"
},
"pio": {
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"mode": "I8259Slave",
"cxx_class": "X86ISA::I8259",
"path": "system.pc.south_bridge.pic2",
"pio_addr": 9223372036854775968,
"type": "I8259"
},
"dma1": {
"name": "dma1",
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "X86ISA::I8237",
"path": "system.pc.south_bridge.dma1",
"pio_addr": 9223372036854775808,
"type": "I8237"
},
"eventq_index": 0,
"cxx_class": "SouthBridge",
"path": "system.pc.south_bridge",
"ide": {
"PMCAPNextCapability": 0,
"InterruptPin": 1,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"pio_latency": 3.0000000000000004e-08,
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 3,
"PXCAPCapabilities": 0,
"SubsystemID": 0,
"PXCAPCapId": 0,
"BAR4": 1,
"BAR1": 1012,
"BAR0": 496,
"BAR3": 884,
"BAR2": 368,
"BAR5": 1,
"PXCAPDevStatus": 0,
"disks": [
{
"driveID": "master",
"name": "disks0",
"image": {
"read_only": false,
"name": "image",
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image.child",
"type": "RawDiskImage"
},
"eventq_index": 0,
"cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image",
"table_size": 65536,
"type": "CowDiskImage"
},
"delay": 1e-06,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks0",
"type": "IdeDisk"
},
{
"driveID": "master",
"name": "disks1",
"image": {
"read_only": false,
"name": "image",
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image.child",
"type": "RawDiskImage"
},
"eventq_index": 0,
"cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image",
"table_size": 65536,
"type": "CowDiskImage"
},
"delay": 1e-06,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks1",
"type": "IdeDisk"
}
],
"BAR2Size": 8,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": true,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"Command": 0,
"SubClassCode": 1,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 0,
"InterruptLine": 14,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": true,
"BAR4Size": 16,
"path": "system.pc.south_bridge.ide",
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 8,
"name": "ide",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"type": "IdeController",
"ctrl_offset": 0,
"PXCAPBaseOffset": 0,
"DeviceID": 28945,
"io_shift": 0,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[1]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"config_latency": 2e-08,
"BAR1Size": 3,
"pio": {
"peer": "system.iobus.master[3]",
"role": "SLAVE"
},
"pci_dev": 4,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[4]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": true,
"ProgIF": 128,
"BAR1LegacyIO": true,
"PMCAPCapabilities": 0,
"ClassCode": 1
},
"type": "SouthBridge",
"cmos": {
"name": "cmos",
"pio": {
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.cmos.int_pin",
"type": "X86IntSourcePin",
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
"time": "Sun Jan 1 00:00:00 2012",
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "X86ISA::Cmos",
"path": "system.pc.south_bridge.cmos",
"pio_addr": 9223372036854775920,
"type": "Cmos"
}
},
"fake_floppy": {
"ret_data8": 255,
"name": "fake_floppy",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 2,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.fake_floppy",
"pio_addr": 9223372036854776818,
"type": "IsaFake",
"ret_data16": 65535
},
"com_1": {
"name": "com_1",
"pio": {
"peer": "system.iobus.master[13]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"terminal": {
"name": "terminal",
"output": true,
"number": 0,
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.pc.com_1.terminal",
"type": "Terminal",
"port": 3456
},
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.pc.com_1",
"pio_addr": 9223372036854776824,
"type": "Uart8250"
},
"eventq_index": 0,
"cxx_class": "Pc",
"path": "system.pc",
"behind_pci": {
"ret_data8": 255,
"name": "behind_pci",
"pio": {
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.behind_pci",
"pio_addr": 9223372036854779128,
"type": "IsaFake",
"ret_data16": 65535
},
"type": "Pc",
"i_dont_exist": {
"ret_data8": 255,
"name": "i_dont_exist",
"pio": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 1,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.i_dont_exist",
"pio_addr": 9223372036854775936,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_com_3": {
"ret_data8": 255,
"name": "fake_com_3",
"pio": {
"peer": "system.iobus.master[15]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.pc.fake_com_3",
"pio_addr": 9223372036854776808,
"type": "IsaFake",
"ret_data16": 65535
}
},
"eventq_index": 0,
"e820_table": {
"name": "e820_table",
"cxx_class": "X86ISA::E820Table",
"eventq_index": 0,
"entries": [
{
"addr": 0,
"range_type": 1,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries0",
"size": 654336,
"type": "X86E820Entry",
"name": "entries0"
},
{
"addr": 654336,
"range_type": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries1",
"size": 394240,
"type": "X86E820Entry",
"name": "entries1"
},
{
"addr": 1048576,
"range_type": 1,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries2",
"size": 133169152,
"type": "X86E820Entry",
"name": "entries2"
},
{
"addr": 4294901760,
"range_type": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries3",
"size": 65536,
"type": "X86E820Entry",
"name": "entries3"
}
],
"path": "system.e820_table",
"type": "X86E820Table"
},
"acpi_description_table_pointer": {
"name": "acpi_description_table_pointer",
"xsdt": {
"name": "xsdt",
"creator_revision": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::ACPI::XSDT",
"path": "system.acpi_description_table_pointer.xsdt",
"oem_revision": 0,
"type": "X86ACPIXSDT"
},
"eventq_index": 0,
"cxx_class": "X86ISA::ACPI::RSDP",
"path": "system.acpi_description_table_pointer",
"type": "X86ACPIRSDP",
"revision": 2
},
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"transition_latency": 9.999999999999999e-05,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "LinuxX86System",
"voltage_domain": {
"eventq_index": 0,
"path": "system.voltage_domain",
"type": "VoltageDomain",
"name": "voltage_domain",
"cxx_class": "VoltageDomain"
},
"cache_line_size": 64,
"intel_mp_pointer": {
"imcr_present": true,
"name": "intel_mp_pointer",
"spec_rev": 4,
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::FloatingPointer",
"path": "system.intel_mp_pointer",
"type": "X86IntelMPFloatingPointer",
"default_config": 0
},
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"init_perf_level": 0,
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"toL2Bus": {
"slave": {
"peer": [
"system.cpu0.icache.mem_side",
"system.cpu0.dcache.mem_side",
"system.cpu0.itb.walker.port",
"system.cpu0.dtb.walker.port"
],
"role": "SLAVE"
},
"name": "toL2Bus",
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.l2c.cpu_side"
],
"role": "MASTER"
},
"cxx_class": "CoherentBus",
"path": "system.toL2Bus",
"type": "CoherentBus",
"use_default_range": false
},
"iocache": {
"assoc": 8,
"mem_side": {
"peer": "system.membus.slave[4]",
"role": "MASTER"
},
"cpu_side": {
"peer": "system.iobus.master[18]",
"role": "SLAVE"
},
"name": "iocache",
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 50,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"path": "system.iocache.tags",
"block_size": 64,
"type": "LRU",
"size": 1024
},
"hit_latency": 50,
"mshrs": 20,
"response_latency": 50,
"is_top_level": true,
"tgts_per_mshr": 12,
"sequential_access": false,
"max_miss_count": 0,
"eventq_index": 0,
"prefetch_on_access": false,
"cxx_class": "BaseCache",
"path": "system.iocache",
"write_buffers": 8,
"two_queue": false,
"type": "BaseCache",
"forward_snoops": false,
"size": 1024
},
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"system_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"load_addr_mask": 18446744073709551615,
"cpu": [
{
"simpoint_interval": 100000000,
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.itb.walker",
"type": "X86PagetableWalker",
"port": {
"peer": "system.toL2Bus.slave[2]",
"role": "MASTER"
},
"num_squash_per_cycle": 4
},
"path": "system.cpu0.itb",
"type": "X86TLB",
"size": 64
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"apic_clk_domain": {
"name": "apic_clk_domain",
"eventq_index": 0,
"cxx_class": "DerivedClockDomain",
"path": "system.cpu0.apic_clk_domain",
"type": "DerivedClockDomain",
"clk_divider": 16
},
"simpoint_profile": false,
"simulate_data_stalls": false,
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"eventq_index": 0,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0.0,
"icache_port": {
"peer": "system.cpu0.icache.cpu_side",
"role": "MASTER"
},
"icache": {
"assoc": 1,
"mem_side": {
"peer": "system.toL2Bus.slave[0]",
"role": "MASTER"
},
"cpu_side": {
"peer": "system.cpu0.icache_port",
"role": "SLAVE"
},
"name": "icache",
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
"sequential_access": false,
"assoc": 1,
"cxx_class": "LRU",
"path": "system.cpu0.icache.tags",
"block_size": 64,
"type": "LRU",
"size": 32768
},
"hit_latency": 2,
"mshrs": 4,
"response_latency": 2,
"is_top_level": true,
"tgts_per_mshr": 20,
"sequential_access": false,
"max_miss_count": 0,
"eventq_index": 0,
"prefetch_on_access": false,
"cxx_class": "BaseCache",
"path": "system.cpu0.icache",
"write_buffers": 8,
"two_queue": false,
"type": "BaseCache",
"forward_snoops": true,
"size": 32768
},
"interrupts": {
"int_master": {
"peer": "system.membus.slave[3]",
"role": "MASTER"
},
"name": "interrupts",
"pio": {
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"int_slave": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
"int_latency": 1e-09,
"eventq_index": 0,
"cxx_class": "X86ISA::Interrupts",
"path": "system.cpu0.interrupts",
"pio_addr": 2305843009213693952,
"type": "X86LocalApic"
},
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu0",
"isa": [
{
"eventq_index": 0,
"path": "system.cpu0.isa",
"type": "X86ISA",
"name": "isa",
"cxx_class": "X86ISA::ISA"
}
],
"switched_out": false,
"name": "cpu0",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.dtb.walker",
"type": "X86PagetableWalker",
"port": {
"peer": "system.toL2Bus.slave[3]",
"role": "MASTER"
},
"num_squash_per_cycle": 4
},
"path": "system.cpu0.dtb",
"type": "X86TLB",
"size": 64
},
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0.0,
"dcache_port": {
"peer": "system.cpu0.dcache.cpu_side",
"role": "MASTER"
},
"dcache": {
"assoc": 4,
"mem_side": {
"peer": "system.toL2Bus.slave[1]",
"role": "MASTER"
},
"cpu_side": {
"peer": "system.cpu0.dcache_port",
"role": "SLAVE"
},
"name": "dcache",
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
"sequential_access": false,
"assoc": 4,
"cxx_class": "LRU",
"path": "system.cpu0.dcache.tags",
"block_size": 64,
"type": "LRU",
"size": 32768
},
"hit_latency": 2,
"mshrs": 4,
"response_latency": 2,
"is_top_level": true,
"tgts_per_mshr": 20,
"sequential_access": false,
"max_miss_count": 0,
"eventq_index": 0,
"prefetch_on_access": false,
"cxx_class": "BaseCache",
"path": "system.cpu0.dcache",
"write_buffers": 8,
"two_queue": false,
"type": "BaseCache",
"forward_snoops": true,
"size": 32768
},
"max_loads_any_thread": 0,
"tracer": {
"eventq_index": 0,
"path": "system.cpu0.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
},
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.itb.walker",
"type": "X86PagetableWalker",
"num_squash_per_cycle": 4
},
"path": "system.cpu1.itb",
"type": "X86TLB",
"size": 64
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"function_trace_start": 0,
"cpu_id": 0,
"eventq_index": 0,
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0.0,
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu1",
"isa": [
{
"eventq_index": 0,
"path": "system.cpu1.isa",
"type": "X86ISA",
"name": "isa",
"cxx_class": "X86ISA::ISA"
}
],
"switched_out": true,
"name": "cpu1",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.dtb.walker",
"type": "X86PagetableWalker",
"num_squash_per_cycle": 4
},
"path": "system.cpu1.dtb",
"type": "X86TLB",
"size": 64
},
"max_insts_any_thread": 0,
"progress_interval": 0.0,
"max_loads_any_thread": 0,
"tracer": {
"eventq_index": 0,
"path": "system.cpu1.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
},
{
"SQEntries": 32,
"smtLSQThreshold": 100,
"do_statistics_insts": true,
"dispatchWidth": 8,
"iewToRenameDelay": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.itb.walker",
"type": "X86PagetableWalker",
"num_squash_per_cycle": 4
},
"path": "system.cpu2.itb",
"type": "X86TLB",
"size": 64
},
"wbWidth": 8,
"squashWidth": 8,
"forwardComSize": 5,
"function_trace": false,
"do_checkpoint_insts": true,
"fetchWidth": 8,
"cxx_class": "DerivO3CPU",
"backComSize": 5,
"switched_out": true,
"max_loads_all_threads": 0,
"numROBEntries": 192,
"commitToIEWDelay": 1,
"commitToDecodeDelay": 1,
"decodeToRenameDelay": 1,
"fetchToDecodeDelay": 1,
"issueWidth": 8,
"LSQCheckLoads": true,
"commitToRenameDelay": 1,
"renameToDecodeDelay": 1,
"wbDepth": 1,
"fuPool": {
"name": "fuPool",
"FUList": [
{
"count": 6,
"opList": [
{
"issueLat": 1,
"opLat": 1,
"name": "opList",
"eventq_index": 0,
"opClass": "IntAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList0.opList",
"type": "OpDesc"
}
],
"name": "FUList0",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList0",
"type": "FUDesc"
},
{
"count": 2,
"opList": [
{
"issueLat": 1,
"opLat": 3,
"name": "opList0",
"eventq_index": 0,
"opClass": "IntMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList1.opList0",
"type": "OpDesc"
},
{
"issueLat": 19,
"opLat": 20,
"name": "opList1",
"eventq_index": 0,
"opClass": "IntDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList1.opList1",
"type": "OpDesc"
}
],
"name": "FUList1",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList1",
"type": "FUDesc"
},
{
"count": 4,
"opList": [
{
"issueLat": 1,
"opLat": 2,
"name": "opList0",
"eventq_index": 0,
"opClass": "FloatAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList0",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 2,
"name": "opList1",
"eventq_index": 0,
"opClass": "FloatCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList1",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 2,
"name": "opList2",
"eventq_index": 0,
"opClass": "FloatCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList2",
"type": "OpDesc"
}
],
"name": "FUList2",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList2",
"type": "FUDesc"
},
{
"count": 2,
"opList": [
{
"issueLat": 1,
"opLat": 4,
"name": "opList0",
"eventq_index": 0,
"opClass": "FloatMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList0",
"type": "OpDesc"
},
{
"issueLat": 12,
"opLat": 12,
"name": "opList1",
"eventq_index": 0,
"opClass": "FloatDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList1",
"type": "OpDesc"
},
{
"issueLat": 24,
"opLat": 24,
"name": "opList2",
"eventq_index": 0,
"opClass": "FloatSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList2",
"type": "OpDesc"
}
],
"name": "FUList3",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList3",
"type": "FUDesc"
},
{
"count": 0,
"opList": [
{
"issueLat": 1,
"opLat": 1,
"name": "opList",
"eventq_index": 0,
"opClass": "MemRead",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList4.opList",
"type": "OpDesc"
}
],
"name": "FUList4",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList4",
"type": "FUDesc"
},
{
"count": 4,
"opList": [
{
"issueLat": 1,
"opLat": 1,
"name": "opList00",
"eventq_index": 0,
"opClass": "SimdAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList00",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList01",
"eventq_index": 0,
"opClass": "SimdAddAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList01",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList02",
"eventq_index": 0,
"opClass": "SimdAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList02",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList03",
"eventq_index": 0,
"opClass": "SimdCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList03",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList04",
"eventq_index": 0,
"opClass": "SimdCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList04",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList05",
"eventq_index": 0,
"opClass": "SimdMisc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList05",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList06",
"eventq_index": 0,
"opClass": "SimdMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList06",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList07",
"eventq_index": 0,
"opClass": "SimdMultAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList07",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList08",
"eventq_index": 0,
"opClass": "SimdShift",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList08",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList09",
"eventq_index": 0,
"opClass": "SimdShiftAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList09",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList10",
"eventq_index": 0,
"opClass": "SimdSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList10",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList11",
"eventq_index": 0,
"opClass": "SimdFloatAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList11",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList12",
"eventq_index": 0,
"opClass": "SimdFloatAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList12",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList13",
"eventq_index": 0,
"opClass": "SimdFloatCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList13",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList14",
"eventq_index": 0,
"opClass": "SimdFloatCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList14",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList15",
"eventq_index": 0,
"opClass": "SimdFloatDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList15",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList16",
"eventq_index": 0,
"opClass": "SimdFloatMisc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList16",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList17",
"eventq_index": 0,
"opClass": "SimdFloatMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList17",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList18",
"eventq_index": 0,
"opClass": "SimdFloatMultAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList18",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList19",
"eventq_index": 0,
"opClass": "SimdFloatSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList19",
"type": "OpDesc"
}
],
"name": "FUList5",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList5",
"type": "FUDesc"
},
{
"count": 0,
"opList": [
{
"issueLat": 1,
"opLat": 1,
"name": "opList",
"eventq_index": 0,
"opClass": "MemWrite",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList6.opList",
"type": "OpDesc"
}
],
"name": "FUList6",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList6",
"type": "FUDesc"
},
{
"count": 4,
"opList": [
{
"issueLat": 1,
"opLat": 1,
"name": "opList0",
"eventq_index": 0,
"opClass": "MemRead",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList7.opList0",
"type": "OpDesc"
},
{
"issueLat": 1,
"opLat": 1,
"name": "opList1",
"eventq_index": 0,
"opClass": "MemWrite",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList7.opList1",
"type": "OpDesc"
}
],
"name": "FUList7",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList7",
"type": "FUDesc"
},
{
"count": 1,
"opList": [
{
"issueLat": 3,
"opLat": 3,
"name": "opList",
"eventq_index": 0,
"opClass": "IprAccess",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList8.opList",
"type": "OpDesc"
}
],
"name": "FUList8",
"eventq_index": 0,
"cxx_class": "FUDesc",
"path": "system.cpu2.fuPool.FUList8",
"type": "FUDesc"
}
],
"eventq_index": 0,
"cxx_class": "FUPool",
"path": "system.cpu2.fuPool",
"type": "FUPool"
},
"cachePorts": 200,
"function_trace_start": 0,
"cpu_id": 0,
"store_set_clear_period": 250000,
"numPhysFloatRegs": 256,
"eventq_index": 0,
"smtNumFetchingThreads": 1,
"numThreads": 1,
"numPhysIntRegs": 256,
"do_quiesce": true,
"type": "DerivO3CPU",
"isa": [
{
"eventq_index": 0,
"path": "system.cpu2.isa",
"type": "X86ISA",
"name": "isa",
"cxx_class": "X86ISA::ISA"
}
],
"smtROBThreshold": 100,
"profile": 0.0,
"renameToROBDelay": 1,
"commitToFetchDelay": 1,
"fetchTrapLatency": 1,
"progress_interval": 0.0,
"commitWidth": 8,
"branchPred": {
"choiceCtrBits": 2,
"name": "branchPred",
"globalCtrBits": 2,
"numThreads": 1,
"localHistoryTableSize": 2048,
"choicePredictorSize": 8192,
"instShiftAmt": 2,
"localCtrBits": 2,
"eventq_index": 0,
"BTBTagSize": 16,
"BTBEntries": 4096,
"cxx_class": "BPredUnit",
"path": "system.cpu2.branchPred",
"localPredictorSize": 2048,
"type": "BranchPredictor",
"RASSize": 16,
"globalPredictorSize": 8192
},
"socket_id": 0,
"numPhysCCRegs": 1280,
"renameToFetchDelay": 1,
"LSQDepCheckShift": 4,
"decodeWidth": 8,
"trapLatency": 13,
"needsTSO": true,
"renameWidth": 8,
"path": "system.cpu2",
"max_insts_all_threads": 0,
"max_loads_any_thread": 0,
"numRobs": 1,
"iewToDecodeDelay": 1,
"max_insts_any_thread": 0,
"issueToExecuteDelay": 1,
"name": "cpu2",
"fetchBufferSize": 64,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.dtb.walker",
"type": "X86PagetableWalker",
"num_squash_per_cycle": 4
},
"path": "system.cpu2.dtb",
"type": "X86TLB",
"size": 64
},
"SSITSize": 1024,
"LQEntries": 32,
"numIQEntries": 64,
"activity": 0,
"LFSTSize": 1024,
"iewToCommitDelay": 1,
"renameToIEWDelay": 2,
"iewToFetchDelay": 1,
"tracer": {
"eventq_index": 0,
"path": "system.cpu2.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
},
"decodeToFetchDelay": 1,
"smtIQThreshold": 100
}
],
"intrctrl": {
"eventq_index": 0,
"path": "system.intrctrl",
"type": "IntrControl",
"name": "intrctrl",
"cxx_class": "IntrControl"
},
"num_work_ids": 16,
"work_item_id": -1,
"work_begin_cpu_id_exit": -1
},
"time_sync_period": 0.1,
"eventq_index": 0,
"time_sync_spin_threshold": 9.999999999999999e-05,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": true
}