1578d2d0b6
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209
98 lines
3.4 KiB
C++
98 lines
3.4 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Mitch Hayenga
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*/
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#ifndef __CPU_PRED_INDIRECT_HH__
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#define __CPU_PRED_INDIRECT_HH__
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#include <deque>
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/inst_seq.hh"
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class IndirectPredictor
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{
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public:
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IndirectPredictor(bool hash_ghr, bool hash_targets,
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unsigned num_sets, unsigned num_ways,
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unsigned tag_bits, unsigned path_len,
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unsigned inst_shift, unsigned num_threads);
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bool lookup(Addr br_addr, unsigned ghr, TheISA::PCState& br_target,
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ThreadID tid);
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void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
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ThreadID tid);
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void commit(InstSeqNum seq_num, ThreadID tid);
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void squash(InstSeqNum seq_num, ThreadID tid);
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void recordTarget(InstSeqNum seq_num, unsigned ghr,
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const TheISA::PCState& target, ThreadID tid);
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private:
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const bool hashGHR;
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const bool hashTargets;
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const unsigned numSets;
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const unsigned numWays;
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const unsigned tagBits;
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const unsigned pathLength;
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const unsigned instShift;
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struct IPredEntry
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{
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IPredEntry() : tag(0), target(0) { }
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Addr tag;
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TheISA::PCState target;
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};
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std::vector<std::vector<IPredEntry> > targetCache;
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Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
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Addr getTag(Addr br_addr);
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struct HistoryEntry
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{
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HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
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: pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
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Addr pcAddr;
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Addr targetAddr;
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InstSeqNum seqNum;
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};
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struct ThreadInfo {
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ThreadInfo() : headHistEntry(0) { }
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std::deque<HistoryEntry> pathHist;
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unsigned headHistEntry;
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};
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std::vector<ThreadInfo> threadInfo;
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};
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#endif // __CPU_PRED_INDIRECT_HH__
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