1578d2d0b6
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209
186 lines
6.1 KiB
C++
186 lines
6.1 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Mitch Hayenga
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*/
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#include "cpu/pred/indirect.hh"
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#include "base/intmath.hh"
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#include "debug/Indirect.hh"
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IndirectPredictor::IndirectPredictor(bool hash_ghr, bool hash_targets,
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unsigned num_sets, unsigned num_ways,
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unsigned tag_bits, unsigned path_len, unsigned inst_shift,
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unsigned num_threads)
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: hashGHR(hash_ghr), hashTargets(hash_targets),
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numSets(num_sets), numWays(num_ways), tagBits(tag_bits),
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pathLength(path_len), instShift(inst_shift)
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{
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if (!isPowerOf2(numSets)) {
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panic("Indirect predictor requires power of 2 number of sets");
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}
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threadInfo.resize(num_threads);
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targetCache.resize(numSets);
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for (unsigned i = 0; i < numSets; i++) {
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targetCache[i].resize(numWays);
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}
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}
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bool
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IndirectPredictor::lookup(Addr br_addr, unsigned ghr, TheISA::PCState& target,
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ThreadID tid)
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{
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Addr set_index = getSetIndex(br_addr, ghr, tid);
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Addr tag = getTag(br_addr);
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assert(set_index < numSets);
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DPRINTF(Indirect, "Looking up %x (set:%d)\n", br_addr, set_index);
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const auto &iset = targetCache[set_index];
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for (auto way = iset.begin(); way != iset.end(); ++way) {
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if (way->tag == tag) {
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DPRINTF(Indirect, "Hit %x (target:%s)\n", br_addr, way->target);
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target = way->target;
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return true;
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}
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}
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DPRINTF(Indirect, "Miss %x\n", br_addr);
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return false;
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}
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void
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IndirectPredictor::recordIndirect(Addr br_addr, Addr tgt_addr,
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InstSeqNum seq_num, ThreadID tid)
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{
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DPRINTF(Indirect, "Recording %x seq:%d\n", br_addr, seq_num);
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HistoryEntry entry(br_addr, tgt_addr, seq_num);
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threadInfo[tid].pathHist.push_back(entry);
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}
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void
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IndirectPredictor::commit(InstSeqNum seq_num, ThreadID tid)
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{
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DPRINTF(Indirect, "Committing seq:%d\n", seq_num);
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ThreadInfo &t_info = threadInfo[tid];
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if (t_info.pathHist.empty()) return;
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if (t_info.headHistEntry < t_info.pathHist.size() &&
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t_info.pathHist[t_info.headHistEntry].seqNum <= seq_num) {
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if (t_info.headHistEntry >= pathLength) {
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t_info.pathHist.pop_front();
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} else {
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++t_info.headHistEntry;
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}
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}
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}
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void
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IndirectPredictor::squash(InstSeqNum seq_num, ThreadID tid)
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{
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DPRINTF(Indirect, "Squashing seq:%d\n", seq_num);
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ThreadInfo &t_info = threadInfo[tid];
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auto squash_itr = t_info.pathHist.begin();
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while (squash_itr != t_info.pathHist.end()) {
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if (squash_itr->seqNum > seq_num) {
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break;
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}
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++squash_itr;
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}
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if (squash_itr != t_info.pathHist.end()) {
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DPRINTF(Indirect, "Squashing series starting with sn:%d\n",
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squash_itr->seqNum);
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}
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t_info.pathHist.erase(squash_itr, t_info.pathHist.end());
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}
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void
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IndirectPredictor::recordTarget(InstSeqNum seq_num, unsigned ghr,
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const TheISA::PCState& target, ThreadID tid)
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{
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ThreadInfo &t_info = threadInfo[tid];
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// Should have just squashed so this branch should be the oldest
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auto hist_entry = *(t_info.pathHist.rbegin());
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// Temporarily pop it off the history so we can calculate the set
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t_info.pathHist.pop_back();
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Addr set_index = getSetIndex(hist_entry.pcAddr, ghr, tid);
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Addr tag = getTag(hist_entry.pcAddr);
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hist_entry.targetAddr = target.instAddr();
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t_info.pathHist.push_back(hist_entry);
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assert(set_index < numSets);
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auto &iset = targetCache[set_index];
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for (auto way = iset.begin(); way != iset.end(); ++way) {
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if (way->tag == tag) {
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DPRINTF(Indirect, "Updating Target (seq: %d br:%x set:%d target:"
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"%s)\n", seq_num, hist_entry.pcAddr, set_index, target);
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way->target = target;
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return;
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}
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}
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DPRINTF(Indirect, "Allocating Target (seq: %d br:%x set:%d target:%s)\n",
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seq_num, hist_entry.pcAddr, set_index, target);
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// Did not find entry, random replacement
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auto &way = iset[rand() % numWays];
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way.tag = tag;
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way.target = target;
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}
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inline Addr
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IndirectPredictor::getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid)
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{
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ThreadInfo &t_info = threadInfo[tid];
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Addr hash = br_addr >> instShift;
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if (hashGHR) {
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hash ^= ghr;
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}
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if (hashTargets) {
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unsigned hash_shift = floorLog2(numSets) / pathLength;
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for (int i = t_info.pathHist.size()-1, p = 0;
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i >= 0 && p < pathLength; i--, p++) {
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hash ^= (t_info.pathHist[i].targetAddr >>
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(instShift + p*hash_shift));
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}
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}
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return hash & (numSets-1);
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}
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inline Addr
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IndirectPredictor::getTag(Addr br_addr)
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{
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return (br_addr >> instShift) & ((0x1<<tagBits)-1);
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}
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