743 lines
85 KiB
Text
743 lines
85 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000037 # Number of seconds simulated
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sim_ticks 37494000 # Number of ticks simulated
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final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 200557 # Simulator instruction rate (inst/s)
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host_op_rate 200498 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1171902214 # Simulator tick rate (ticks/s)
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host_mem_usage 294520 # Number of bytes of host memory used
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host_seconds 0.03 # Real time elapsed on the host
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sim_insts 6413 # Number of instructions simulated
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sim_ops 6413 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
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system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 619619139 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 288472822 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 908091961 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 619619139 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 619619139 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 619619139 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 288472822 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 908091961 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 532 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 73 # Per bank write bursts
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system.physmem.perBankRdBursts::1 39 # Per bank write bursts
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system.physmem.perBankRdBursts::2 36 # Per bank write bursts
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system.physmem.perBankRdBursts::3 54 # Per bank write bursts
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system.physmem.perBankRdBursts::4 45 # Per bank write bursts
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system.physmem.perBankRdBursts::5 21 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1 # Per bank write bursts
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system.physmem.perBankRdBursts::7 5 # Per bank write bursts
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system.physmem.perBankRdBursts::8 0 # Per bank write bursts
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system.physmem.perBankRdBursts::9 1 # Per bank write bursts
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system.physmem.perBankRdBursts::10 21 # Per bank write bursts
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system.physmem.perBankRdBursts::11 29 # Per bank write bursts
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system.physmem.perBankRdBursts::12 19 # Per bank write bursts
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system.physmem.perBankRdBursts::13 127 # Per bank write bursts
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system.physmem.perBankRdBursts::14 47 # Per bank write bursts
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system.physmem.perBankRdBursts::15 14 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 37389500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 532 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 387.902439 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 251.688412 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 333.441746 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 19 23.17% 23.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 18 21.95% 45.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 11 13.41% 58.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 10 12.20% 70.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1 1.22% 71.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6 7.32% 79.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 4 4.88% 84.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 5 6.10% 90.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8 9.76% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
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system.physmem.totQLat 3129000 # Total ticks spent queuing
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system.physmem.totMemAccLat 13104000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 5881.58 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 24631.58 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 908.09 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 908.09 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 7.09 # Data bus utilization in percentage
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system.physmem.busUtilRead 7.09 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 438 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 70281.02 # Average gap between requests
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system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
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system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 16000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 20432790 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ)
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system.physmem_1.averagePower 810.835582 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states
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system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
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system.cpu.branchPred.lookups 2009 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 378 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
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system.cpu.branchPred.indirectLookups 338 # Number of indirect predictor lookups.
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system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
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system.cpu.branchPred.indirectMisses 325 # Number of indirect misses.
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system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1378 # DTB read hits
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system.cpu.dtb.read_misses 11 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1389 # DTB read accesses
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system.cpu.dtb.write_hits 885 # DTB write hits
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|
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 888 # DTB write accesses
|
|
system.cpu.dtb.data_hits 2263 # DTB hits
|
|
system.cpu.dtb.data_misses 14 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 2277 # DTB accesses
|
|
system.cpu.itb.fetch_hits 2687 # ITB hits
|
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 2704 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 74988 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 6413 # Number of instructions committed
|
|
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 11.693123 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.085520 # IPC: instructions per cycle
|
|
system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
|
|
system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
|
|
system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
|
|
system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
|
|
system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction
|
|
system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::total 6413 # Class of committed instruction
|
|
system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1980 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 227 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8280500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8280500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 17445000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 17445000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 17445000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 17445000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2207 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2207 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2207 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2207 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076006 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.076006 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.102855 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.102855 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.102855 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.102855 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81181.372549 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 81181.372549 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 76850.220264 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 76850.220264 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7723000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7723000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13108500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 13108500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13108500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 13108500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071535 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071535 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.076575 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.076575 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.085602 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 5738 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 2323 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 2323 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 2323 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27766000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 27766000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 27766000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 27766000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 27766000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 27766000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2687 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 2687 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 2687 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 2687 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 2687 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 2687 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135467 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.135467 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.135467 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.135467 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.135467 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.135467 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76280.219780 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 76280.219780 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 76280.219780 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 76280.219780 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27402000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 27402000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27402000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 27402000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27402000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 27402000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135467 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.135467 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005351 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001770 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.007121 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 532 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26844000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 26844000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7577500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7577500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 26844000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 12852500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 39696500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 26844000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 12852500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 39696500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73950.413223 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73950.413223 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78932.291667 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78932.291667 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 74617.481203 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23214000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23214000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6617500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6617500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11162500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 34376500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11162500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 34376500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63950.413223 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63950.413223 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 459 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 532 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 532 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
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|
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2826750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
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|
|
|
---------- End Simulation Statistics ----------
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