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Geoffrey Blake 85940fd537 arch, arm: Preserve TLB bootUncacheability when switching CPUs The ARM TLBs have a bootUncacheability flag used to make some loads and stores become uncacheable when booting in FS mode. Later the flag is cleared to let those loads and stores operate as normal. When doing a takeOverFrom(), this flag's state is not preserved and is momentarily reset until the CPSR is touched. On single core runs this is a non-issue. On multi-core runs this can lead to crashes on the O3 CPU model from the following series of events: 1) takeOverFrom executed to switch from Atomic -> O3 2) All bootUncacheability flags are reset to true 3) Core2 tries to execute a load covered by bootUncacheability, it is flagged as uncacheable 4) Core2's load needs to replay due to a pipeline flush 3) Core1 core does an action on CPSR 4) The handling code for CPSR then checks all other cores to determine if bootUncacheability can be set to false 5) Asynchronously set bootUncacheability on all cores to false 6) Core2 replays load previously set as uncacheable and notices it is now flagged as cacheable, leads to a panic. This patch implements takeOverFrom() functionality for the ARM TLBs to preserve flag values when switching from atomic -> detailed.		2014-05-09 18:58:47 -04:00
build_opts	ruby: rename MESI_CMP_directory to MESI_Two_Level	2014-01-04 00:03:33 -06:00
configs	config: ruby: remove memory controller from network test	2014-04-19 09:00:30 -05:00
ext	ext: disable PLY debugging	2014-03-19 19:18:43 -05:00
src	arch, arm: Preserve TLB bootUncacheability when switching CPUs	2014-05-09 18:58:47 -04:00
system	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
tests	mem: Auto-generate CommMonitor trace file names	2014-05-09 18:58:46 -04:00
util	arm: Add Makefile for aarch64 build of util/m5	2014-05-09 18:58:46 -04:00
.hgignore	mem: Add a wrapped DRAMSim2 memory controller	2014-02-18 05:50:53 -05:00
.hgtags	Added tag stable_2014_02_15 to the changeset 459491344fcf	2014-02-15 12:44:09 -06:00
COPYING	copyright: Add code for finding all copyright blocks and create a COPYING file	2011-06-02 17:36:07 -07:00
LICENSE	copyright: Add code for finding all copyright blocks and create a COPYING file	2011-06-02 17:36:07 -07:00
README	gem5: Update the README file to be a bit less out-of-date.	2012-09-25 11:49:40 -05:00
SConstruct	scons: Require SWIG >= 2.0.4 and remove vector typemaps	2014-05-09 18:58:46 -04:00

README

This is the gem5 simulator.

For detailed information about building the simulator and getting
started please refer to:
* The main website:     http://www.gem5.org
* Documentation wiki:   http://www.gem5.org/Documentation 
* Doxygen generated:    http://www.gem5.org/docs
* Tutorials:            http://www.gem5.org/Tutorials


Specific pages of interest are:
http://www.gem5.org/Introduction
http://www.gem5.org/Build_System
http://www.gem5.org/Dependencies
http://www.gem5.org/Running_gem5

Short version:
External tools and required versions

To build gem5, you will need the following software:
g++ version 4.3 or newer.
Python, version 2.4 - 2.7 (we don't support Python 3.X). gem5 links in the 
    Python interpreter, so you need the Python header files and shared 
    library (e.g., /usr/lib/libpython2.4.so) in addition to the interpreter
    executable. These may or may not be installed by default. For example,
    on Debian/Ubuntu, you need the "python-dev" package in addition to the
    "python" package. If you need a newer or different Python installation
     but can't or don't want to upgrade the default Python on your system,
     see http://www.gem5.org/Using_a_non-default_Python_installation
SCons, version 0.98.1 or newer. SCons is a powerful replacement for make. 
    If you don't have administrator privileges on your machine, you can use the
    "scons-local" package to install scons in your m5 directory, or install SCons
    in your home directory using the '--prefix=' option.  
SWIG, version 1.3.34 or newer
zlib, any recent version. For Debian/Ubuntu, you will need the "zlib-dev" or
    "zlib1g-dev" package to get the zlib.h header file as well as the library
    itself.
m4, the macro processor.


4. In this directory, type 'scons build/<ARCH>/gem5.opt' where ARCH is one
of ALPHA, ARM, MIPS, POWER, SPARC, or X86. This will build an optimized version
of the gem5 binary (gem5.opt) for the the specified architecture.

If you have questions, please send mail to gem5-users@gem5.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - gem5:
   - configs: example simulation configuration scripts
   - ext: less-common external packages needed to build gem5
   - src: source code of the gem5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk images. 
Please see the gem5 download page for these items at http://www.gem5.org/Download